Power pin to power pin electro-static discharge (ESD) clamp
An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.
1. An integrated circuit including an electrostatic discharge circuit, the integrated circuit having at least two power supply rails, comprising:
a first electrostatic discharge event detection circuit connected to a first power supply rail;
a second electrostatic discharge event detection circuit connected to a second power supply rail;
a first field effect transistor having a channel, said channel connected between said first power supply rail and said second power supply rail;
a second field effect transistor having a channel, said channel connected between a gate of said first field effect transistor and one of said first power supply rail and said second power supply rail;
at least one inverter stage having an output, said output connected to a gate of said second field effect transistor; and
a gate control circuit operative to selectively connect the gate of said first field effect transistor to a common ground of said first power supply rail in response to the first power supply rail being at least equal to a transistor threshold voltage level and to selectively connect the gate of said first field effect transistor to a common ground of said second power supply rail in response to the second power supply rail being at least equal to the transistor threshold voltage level.
2. The integrated circuit according to claim 1 , wherein:
said first power supply rail is connected directly to a first pin external to said integrated circuit; and
said second power supply rail is connected directly to a second pin external to said integrated circuit.
3. The integrated circuit according to claim 1 , wherein
the gate control circuit comprises:
at least third and fourth field effect transistors, the third field effect transistor having a channel connected between the gate of said first field effect transistor and the common ground of said first power supply rail and having a gate coupled to the first power supply rail through a first resistance, the fourth field effect transistor having a channel connected between the gate of said first field effect transistor and the common ground of said second power supply rail and having a gate coupled to the second power supply rail through a second resistance.
4. The integrated circuit according to claim 1 , wherein said at least one inverter stage comprises:
a series connection of a plurality of inverters;
wherein said second field effect transistor is switched to a conductive state during an electrostatic discharge event by a last stage inverter of said plurality of inverters.
5. The integrated circuit according to claim 4 , further comprising:
an RC circuit connected to an input of a first stage of said plurality of inverters, to maintain a logic HIGH level on said input during normal operation of said integrated circuit.
6. The integrated circuit according to claim 4 , wherein:
said plurality of inverters comprises at least three inverters.
7. The integrated circuit according to claim 1 , further comprising:
an electrostatic discharge diode function connected between said first power supply rail and a ground.
8. The integrated circuit according to claim 1 , further comprising:
an electrostatic discharge diode function connected between said second power supply rail and a ground.
9. The integrated circuit according to claim 1 , wherein:
said first power supply rail and said second power supply rail have a common ground.
10. The integrated circuit according to claim 1 , wherein:
said first field effect transistor is a metal oxide semiconductor field effect transistor (MOSFET).
11. The integrated circuit according to claim 10 , wherein:
said MOSFET is an n-type MOSFET.
12. The integrated circuit according to claim 11 , wherein:
said n-type MOSFET has a device width of between 1000 microns and 10,000 microns.
13. The integrated circuit according to claim 11 , wherein:
said n-type MOSFET has a device width of between about 5000 microns and about 6000 microns.
14. The integrated circuit according to claim 1 , wherein:
voltage levels of the first and second power supply rails are not the same at the same time.
15. A method of clamping an electrostatic discharge pulse in an integrated circuit having at least first and second power supply rails, said method comprising:
sensing an electrostatic discharge event on at least one of said at least first and second power supply rails;
in response to said sensing said electrostatic discharge event, biasing a gate of a first field effect transistor having a channel connected between said at least first and second power supply rails;
switching the channel of said first field effect transistor to a conductive state with biasing from a channel of a second field effect transistor connected between said gate of said first field effect transistor and one of said at least first and second power supply rails;
biasing a gate of said second field effect transistor with an output of at least one inverter stage; and
switching the gate of said first field effect transistor to a common ground of said first power supply rail in response to the first power supply rail being at least equal to a transistor threshold voltage level and switching the gate of said first field effect transistor to a common ground of said second power supply rail in response to the second power supply rail being at least equal to the transistor threshold voltage level.
16. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 15 , wherein:
switching the gate of said first field effect transistor to a common ground of said at least first and second power supply rails is performed during normal operation of said integrated circuit.
17. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 15 , wherein:
said first field effect transistor is a metal oxide semiconductor field effect transistor (MOSFET).
18. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 17 , wherein:
said MOSFET is an n-type MOSFET.
19. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 18 , wherein:
said n-type MOSFET has a device width of between 1000 microns and 10,000 microns.
20. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 18 , wherein:
said n-type MOSFET has a device width of between about 5000 microns and about 6,000 microns.
21. The method of clamping an electrostatic discharge pulse in an integrated circuit according to claim 15 , wherein:
said channel of said first field effect transistor is connected directly across said at least first and second power supply rails.
22. Apparatus for clamping an electrostatic discharge pulse in an integrated circuit having at least first and second power supply rails, comprising:
means for sensing an electrostatic discharge event on at least one of said at least first and second power supply rails;
means for biasing, in response to said sensing an electrostatic discharge event, a gate of a first field effect transistor having a channel connected between said at least first and second power supply rails;
means for switching a channel of said first field effect transistor to a conductive state with biasing from a channel of a second field effect transistor connected between said gate of said first field effect transistor and one of said at least first and second power supply rails;
means for biasing a gate of said second field effect transistor with an output of at least one inverter stage; and
means for switching the gate of said first field effect transistor to a common ground of said first power supply rail in response to the first power supply rail being at least equal to a transistor threshold voltage level and for switching the gate of said first field effect transistor to a common ground of said second power supply rail in response to the second power supply rail being at least equal to the transistor threshold voltage level.
23. The apparatus for clamping an electrostatic discharge pulse in an integrated circuit according to claim 22 , wherein:
said means for switching the gate of said first field effect transistor to a common ground of said first and second power supply rails is performed during normal operation of said integrated circuit.
24. The apparatus for clamping an electrostatic discharge pulse in an integrated circuit according to claim 22 , wherein:
voltage levels of two of the at least first and second power supply rails are not the same at the same time.
25. The apparatus for clamping an electrostatic discharge pulse in an integrated circuit according to claim 22 , further comprising:
said channel of said first field effect transistor being connected directly across said at least first and second power supply rails.