Homoepitaxial growth of SiC on low off-axis SiC wafers

1. A method for producing, on an SiC substrate, SiC homoepitaxial layers of the same polytype as said substrate, comprising:

growing said layers on a surface of the SiC substrate, wherein said surface is inclined relative to the (0001) basal plane at an angle higher than 0.1 degree but less than 1 degree,

starting an homoepitaxial growth by forming a boundary layer with a thickness up to 1 μm, and

forming a homoepitaxial device layer wherein said boundary layer is formed in an atmosphere of lower supersaturation than when forming the homoepitaxial device layer and at a C/Si ratio above 1.

2. The method according to claim 1 , further comprising:

growing said boundary layer at an average growth rate being less than 3 μm/h.

3. The method according to claim 1 , further comprising:

predetermining flow rates for Silicon and Carbon precursor gases for the growth of a homoepitaxial device layer and

forming the boundary layer in an atmosphere of lower supersaturation than when forming the device layer by means of injecting into said atmosphere at least one of said Silicon and Carbon precursor gases at a lower flow rate than said respective predetermined flow rate.

4. The method according to claim 1 , wherein said substrate is of hexagonal polytype, the method further comprising:

polishing, chemically and mechanically, the surface of the C-face of said substrate of hexagonal polytype and

growing the homoepitaxial layer on said C-face.

5. The method according to claim 1 , wherein said substrate is of hexagonal polytype, the method further comprising:

polishing, chemically and mechanically, the surface of the Si-face of said substrate of hexagonal polytype and

growing the homoepitaxial layer on said Si-face.

6. The method according to claim 4 , further comprising:

chemical-mechanical polishing said surface to achieve a surface roughness (RMS)<1 Å.

7. The method according to claim 1 , further comprising:

minimizing an etching of the growth surface during heating by introducing, above 1420° C., an Si precursor gas flow scaled to the partial pressure of Si above the SiC growth surface.

8. The method according to claim 1 , further comprising:

providing said boundary layer with a doping of any kind from the group of: n-type, p-type or deep levels provided by intrinsic defects or transition metals.

9. The method according to claim 1 , further comprising:

choosing an off-axis direction along any one from the group of:

one of the 6 equivalent <11 2 0> directions, or

one of the 6 equivalent <01 1 0> directions.

10. The method according to claim 1 , further comprising:

choosing an off-axis direction along: between one of the equivalent <11 2 0> directions and one of the 6 equivalent <01 1 0> directions.

11. The method according to claim 10 , wherein the off-axis direction is within the (0001) plane, at an angle between 10 and 20 degrees of one the equivalent <11 2 0> directions.

12. The method according to claim 1 , further comprising:

growing a buffer layer on top of said boundary layer until the thickness of said buffer layer is at least equal to the tangent of the off-axis angle between the wafer surface and the (0001) basal plane times the width of the device along an off-axis direction.

13. The method according to claim 1 , further comprising:

reducing minority carriers in the boundary layer by introducing during epitaxial growth, or after epitaxial growth, deep levels acting as lifetime killers by means of either transition metals doping, or intrinsic in-grown defects or ex-situ generated intrinsic defects by electron or proton irradiation techniques.

14. The method according to claim 1 , wherein the boundary layer is grown at a Carbon/Silicon ratio optimized for a layer thickness and doping uniformity of a device layer.