IP Library Granted Patent US 7,531,459
Granted Patent B2
US 7,531,459 · App. 11/452,042 · Granted May 12, 2009

Methods of forming self-aligned silicide layers using multiple thermal processes

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,531,459
App. No.
11/452,042
Granted
May 12, 2009
Kind
B2
Abstract

Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.

Claims (36)

1. A method of forming a metal salicide layer comprising:

forming a metal layer on a substrate;

forming a metal silicide layer on the metal layer using a first thermal process at a first temperature; and then

performing, in-situ with the first thermal process, a second thermal process on the metal layer at second temperature that is less than the first temperature.

2. A method according to claim 1 wherein the metal layer comprises a nickel layer.

3. A method according to claim 1 wherein the first temperature is about 300 to about 600° C.

4. A method according to claim 1 wherein the second temperature is about 200 to about 300° C.

5. A method according to claim 1 wherein the second thermal process is performed for about 10 minutes or more.

6. A method according to claim 5 wherein the second thermal process is performed for about 30 minutes or less.

7. A method according to claim 1 further comprising:

removing a non-reacted portion of the metal layer remaining after the second thermal process.

8. A method according to claim 7 further comprising;

performing a third thermal process on the metal silicide layer after removing the non-reacted portion of the metal layer.

9. A method according to claim 8 wherein the third thermal process is performed at a temperature of about 300 to about 600° C.

10. A method according to claim 1 further comprising:

forming a capping layer on the metal layer before forming the metal silicide layer, wherein the capping layer is removed together with a non-reacted portion of the metal layer remaining after forming the metal suicide layer.

11. A method according to claim 1 wherein the substrate is doped with n-type impurity ions.

12. A method of fabricating a semiconductor device, the method comprising:

forming a metal oxide semiconductor (MOS) transistor including source/drain regions separated from each other in a substrate, a gate pattern on a channel region in the substrate between the source/drain regions, and a spacer covering the sidewalls of the gate pattern;

forming a metal layer on the entire surface of the MOS transistor;

forming a metal silicide layer on the metal layer using a first thermal process at a first temperature; and then

performing a second thermal process on the metal layer, in-situ with the first thermal process, at a second temperature that is less than the first temperature.

13. A method according to claim 12 further comprising:

forming a suicide blocking pattern that exposes a top surface of the source/drain regions and/or the gate pattern before forming the metal layer.

14. A method according to claim 12 wherein the gate pattern includes a gate electrode and a gate capping layer.

15. A method according to claim 12 wherein the gate pattern is formed by depositing a polysilicon layer and a tungsten suicide layer or a tungsten layer on the polysilicon layer.

16. A method according to claim 12 wherein the metal layer comprises a nickel layer.

17. A method according to claim 12 wherein the first temperature is about 300 to about 600° C.

18. A method according to claim 12 wherein the second temperature is about 200 to about 300° C.

19. A method according to claim 12 wherein the second thermal process is performed for about 10 minutes or more.

20. A method according to claim 19 wherein the second thermal process is performed for about 30 minutes or less.

21. A method of fabricating a semiconductor device, the method comprising:

performing a silicidation anneal process on a nickel layer on a source/drain region at a first temperature of about 300° C. to about 400° C.; and then

forming a Ni 2 Si layer from the nickel layer using a thermal process to react the nickel layer with silicon in the source/drain region, in-situ with the silicidation anneal process, at second temperature of about 200-300° C. for about 10 to about 30 minutes; and

phase-shifting the Ni 2 Si layer using a thermal process at a temperature of about 400° C. to about 500° C. to form a NiSi layer.

22. A method according to claim 21 wherein each of the performing a silicidation anneal process, forming a Ni 2 Si layer, and phase-shifting the Ni 2 Si is ceased before initiating a subsequent process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2006
From: JUNG, SUG-WOO; CHOI, GIL-HEYUN; KIM, BYUNG-HEE; YUN, JONG-HO; KIM, HYUN-SU; JUNG, EUN-JI
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017993/0933 →
Priority Claims (1)
KR 10-2005-0050528 · Jun 13, 2005 · national
Continuity (1)
Related Publication 20060281305A1 · Dec 14, 2006