Method for forming self-aligned thermal isolation cell for a variable resistance memory array
A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface. ARRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
1. A memory device, comprising:
a via within a dielectric fill;
a lower electrode element;
an upper electrode element;
a bottom spacer element within the via and over the lower electrode element, the bottom spacer element having an inner surface;
a sidewall spacer element on the bottom spacer element, the sidewall spacer element having an inner surface defining an opening substantially centered on the lower electrode element; and
a memory element within the opening defined by the inner surface of the sidewall spacer element and extending between the lower electrode element and the upper electrode element, the memory element spaced away from the inner surface of the bottom spacer element to define a thermal isolation cell.
2. The device of claim 1 , wherein the memory element comprises a combination of Ge, Sb, and Te.
3. The memory device of claim 1 , wherein the memory element comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
4. The memory device of claim 1 , wherein the memory element exhibits variable resistance, such variability being associated with changes in phase structure.
5. The memory device of claim 1 , wherein the bottom spacer element is composed of a material exhibiting high preferential etch properties relative to the sidewall spacer and lower electrode elements.
6. The memory device of claim 1 , wherein the bottom spacer element is composed of tungsten, the sidewall spacer element is composed of a dielectric fill oxide, and the lower electrode element is composed of TiN.
7. The memory device of claim 1 , wherein the upper electrode element extends below a top surface of the sidewall spacer element and into the opening defined by the inner surface of the sidewall spacer element to contact a top surface of the memory element.
8. The memory device of claim 1 , wherein:
the lower electrode element has an outer surface;
the bottom spacer element has an outer surface; and
the sidewall spacer element has an outer surface aligned with the outer surfaces of the bottom spacer element and the lower electrode element.
9. The memory device of claim 8 , wherein the upper electrode element is on a top surface of the dielectric fill.
10. The memory device of claim 9 , wherein:
the sidewall spacer element extends to the top surface of the dielectric fill; and
the upper electrode element extends below the top surface of the dielectric fill and into the opening defined by the inner surface of the sidewall spacer element.
11. The memory device of claim 1 , wherein the bottom spacer element comprises an electrically conductive material.
12. The memory device of claim 1 , wherein:
the lower electrode element is within the via;
the via has a sidewall; and
the sidewall spacer element is on the sidewall of the via.