IP Library › Granted Patent US 7,531,872
Granted Patent B2
US 7,531,872 · App. 11/818,647 · Granted May 12, 2009

High voltage transistor and method for fabricating the same

Assignee: MagnaChip Semiconductor, Ltd.
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Quick Facts
Patent No.
US 7,531,872
App. No.
11/818,647
Granted
May 12, 2009
Kind
B2
Abstract

A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N + -type drain junction region on the insulation layer; an N − -type drain junction region on the N + -type drain junction region; a P − -type body region provided in a trench region of the N − -type drain junction region; a plurality of gate patterns including a gate insulation layer and a gate conductive layer in other trench regions bordered by the P − -type body region and the N − -type drain junction region; a plurality of source regions contacted to a source electrode on the P − -type body region; and a plurality of N + -type drain regions contacted to the N − -type drain junction region and individual drain electrodes.

Claims (16)

1. A high voltage transistor, comprising:

a single insulation layer on a substrate;

an N + -type drain junction region on the single insulation layer;

an N − -type drain junction region on the N + -type drain junction region;

a P − -type body region provided in a first trench region of the N − -type drain junction region;

a plurality of first gate patterns including a first gate insulation layer and a first gate conductive layer in other trench regions bordered by the P − -type body region and the N − -type drain junction region;

a plurality of first source regions contacted to a first source electrode on the P − -type body region;

a plurality of N + -type drain regions contacted to the N − -type drain junction region and individual drain electrodes;

a P + -type drain junction region formed on the single insulation layer, wherein the P + -type drain junction region is formed to be apart from the N + -type drain junction region;

a P − -type drain junction region formed on the P + -type drain junction region;

an N − -type body region provided in a second trench region inside of the P − -type drain junction region;

a plurality of second gate patterns including a second gate insulation layer and a second gate conductive layer in other trench regions bordered by the N − -type body region and the P − -type drain junction region;

a plurality of second source regions contacted to a second source electrode on the N − -type body region; and

a plurality of P + -type drain regions contacted to the P − -type drain junction region and individual drain electrodes.

2. The high voltage transistor of claim 1 , wherein the plurality of first source regions include a P + -type source contact region contacted to the first source electrode and a plurality of N + -type source regions formed in a manner to surround the P + -type source contact region.

3. The high voltage transistor of claim 1 , wherein the plurality of second source regions include an N + -type source contact region contacted to the second source electrode and a plurality of P + -type source regions formed in a manner to surround the N + -type source contact region.

Priority Claims (1)
KR 10-2004-0071818 · Sep 8, 2004 · national
Continuity (2)
Division 1122341300 · Sep 8, 2005
Related Publication 20070252200A1 · Nov 1, 2007