Recessed-type field effect transistor with reduced body effect
For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.
1. A method for fabricating a field effect transistor, comprising:
forming an extra-doped channel region below a surface of a semiconductor substrate;
forming an opening in the semiconductor substrate into the extra-doped channel region to face the extra-doped channel region at a bottom portion of the opening;
forming a gate insulator at walls of the opening such that the extra-doped channel region abuts the gate insulator at the bottom portion of the opening; and
filling the opening with a gate electrode;
wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening,
and wherein the semiconductor substrate instead of the extra-doped channel region abuts the gate insulator at sidewalls of the opening above the half-height of the opening.
2. The method of claim 1 , further comprising:
forming a drain and a source in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
3. The method of claim 2 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
4. The method of claim 2 , further comprising:
forming a respective line pad on each of the drain and the source.
5. The method of claim 4 , further comprising:
forming the field effect transistor as part of a DRAM (dynamic random access memory) cell.
6. The method of claim 5 , wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and wherein the gate electrode forms a word line for the DRAM cell.
7. The method of claim 1 , further comprising:
forming a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.
8. A method for fabricating a field effect transistor, comprising:
forming an extra-doped channel region below a surface of a semiconductor substrate;
forming an opening in the semiconductor substrate into the extra-doped channel region to face the extra-doped channel region at a bottom portion of the opening;
forming a gate insulator at walls of the opening such that the extra-doped channel region abuts the gate insulator at the bottom portion of the opening, and wherein the semiconductor substrate instead of the extra-doped channel region abuts the gate insulator at a top portion of sidewalls of the opening; and
filling the opening with a gate electrode;
wherein the opening is formed after the extra-doped channel region is formed.
9. The method of claim 8 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.
10. The method of claim 8 , further comprising:
forming a drain and a source in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
11. The method of claim 10 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
12. The method of claim 10 , further comprising:
forming a respective line pad on each of the drain and the source.
13. The method of claim 12 , further comprising:
forming the field effect transistor as part of a DRAM (dynamic random access memory) cell, wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and wherein the gate electrode forms a word line for the DRAM cell.
14. The method of claim 8 , further comprising:
forming a gate capping layer on the gate electrode; and
forming spacers on sidewalls of the gate electrode and the gate capping layer.
15. The method of claim 8 , further comprising:
forming a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.
16. A method for fabricating a field effect transistor, comprising:
forming an extra-doped channel region below a surface of a semiconductor substrate;
forming an opening in the semiconductor substrate into the extra-doped channel region to face the extra-doped channel region at a bottom portion of the opening;
forming a gate insulator at walls of the opening such that the extra-doped channel region abuts the gate insulator at the bottom portion of the opening, and wherein the semiconductor substrate instead of the extra-doped channel region abuts the gate insulator at a top portion of sidewalls of the opening;
filling the opening with a gate electrode;
forming a gate capping layer on the gate electrode; and
forming spacers on sidewalls of the gate electrode and the gate capping layer.
17. The method of claim 16 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.
18. The method of claim 16 , further comprising:
forming a drain and a source in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
19. The method of claim 18 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
20. The method of claim 18 , further comprising:
forming a respective line pad on each of the drain and the source;
forming the field effect transistor as part of a DRAM (dynamic random access memory) cell, wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and wherein the gate electrode forms a word line for the DRAM cell.