Advanced process control for semiconductor processing

1. An advanced process control (APC) method for semiconductor fabrication, comprising:

providing a first substrate and a second substrate wherein the first substrate and the second substrate include a dielectric layer;

determining a first etch process parameter for the first substrate;

etching a trench in the dielectric layer of the first substrate using the determined first etch process parameter;

measuring at least one aspect of the etched trench of the first substrate;

determining a second etch process parameter for the second substrate using the at least one measured aspect of the etched trench of the first substrate; and

determining a planarization process parameter for the first substrate using the at least one measured aspect of the etched trench of the first substrate.

2. The method of claim 1 , wherein the method minimizes sheet resistance (Rs) variation.

3. The method of claim 1 , wherein the method controls a damascene copper interconnect fabrication process.

4. The method of claim 1 , wherein the first etch process parameter and the second etch process parameter include trim time.

5. The method of claim 1 , wherein the at least one measured aspect of the etched trench includes at least one of the trench critical dimension and the trench depth.

6. The method of claim 1 , wherein the determining the second etch process parameter is performed by a model-based, run-to-run controller.

7. The method of claim 6 , wherein the controller includes a tool-effect model and a part-effect model.

8. A method for controlling sheet resistance (Rs) variation in semiconductor fabrication, comprising:

providing a first wafer and a second wafer, wherein the first wafer and the second wafer include a dielectric layer;

determining a first etch process parameter for the first wafer;

etching a trench in the dielectric layer of the first wafer using the determined first etch process parameter;

measuring at least one dimension of the etched trench of the first wafer;

determining a second etch process parameter for the second wafer using the at least one measured dimension of the etched trench of the first wafer;

determining a first planarization process parameter for the first wafer using the at least one measured dimension of the etched trench of the first wafer;

depositing metal on the first wafer;

planarizing the first wafer including the metal using the determined first planarization process parameter;

measuring the thickness of the metal on the first wafer after the planarizing; and

determining a second planarization process parameter for the second wafer based on the thickness of the metal on the first wafer after the planarizing.

9. The method of claim 8 , wherein the metal includes copper.

10. The method of claim 8 , wherein the determining the second etch process parameter is performed by a model-based, run-to-run controller, wherein the controller includes a tool-effect model and a part-effect model.

11. The method of claim 8 , wherein the planarizing is performed by a chemical mechanical polish tool and the determined first planarization parameter includes polish time.

12. The method of claim 8 , wherein the determining the second planarization process parameter is performed by a model-based, run-to-run controller.

13. The method of claim 12 , wherein the controller includes a tool-effect model and a part-effect model.

14. The method of claim 13 , wherein the tool-effect model includes a model for the age of a polishing pad of a CMP tool.

15. The method of claim 8 , wherein the depositing metal on the first wafer includes depositing a barrier/seed metal and the determining the first planarization parameter includes using a determined density of the deposited barrier/seed metal.

16. The method of claim 8 , wherein the planarizing the first wafer includes end point detection.