Fin-field effect transistors (Fin-FETs) having protection layers
Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.
1. A Fin-Field Effect Transistor (Fin-FET) comprising:
an integrated circuit substrate having a fin and a trench defining the fin;
a first insulation layer in the trench such that a surface of the first insulation layer is recessed beneath a top surface of the fin exposing sidewalls of the fin;
a protection layer on the first insulation layer; and
a second insulation layer on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.
2. The Fin-FET of claim 1 , wherein the protection layer comprises a lower conformal protection layer in the trench on the sidewalls of the fin and the top surface of the first insulation layer and an upper protection layer on the lower conformal protection layer.
3. The Fin-FET of claim 1 , wherein a top surface of the second insulation layer is recessed beneath the top surface of the fin.
4. The Fin-FET of claim 1 , wherein a top surface of the second insulation layer is higher than the top surface of the fin.
5. The Fin-FET of claim 1 , wherein the fin comprises a plurality of fins, wherein the trench comprises a plurality of trenches and each of the plurality of trenches is defined between the trenches and wherein the plurality of trenches have different widths.
6. The Fin-FET of claim 5 , wherein the plurality of trenches comprises first and second trenches, wherein the first trench has a first width and the second trench has a second width, wider than the first width, and wherein the protection layer comprises a first protection layer filling the first trench having the first width and a second conformal protection layer in the second trench having the second width.
7. The Fin-FET of claim 1 , wherein the protection layer comprises a conformal protection layer in the trench.
8. The Fin-FET of claim 1 , further comprising:
a gate insulation layer on the fin and in the trench; and
a gate electrode on the gate insulation layer.
9. The Fin-FET of claim 1 , further comprising:
a thermal oxidation layer on the sidewalls of the fin and a bottom surface of the trench; and
a liner layer on the thermal oxidation layer.
10. A Fin-Field Effect Transistor (Fin-FET) comprising:
an integrated circuit substrate having a fin and a trench defining the fin;
a first insulation layer in the trench such that a top surface of the first insulation layer is recessed beneath a top surface of the fin exposing sidewalls of the fin;
a protection layer on the first insulation layer; and
a second insulation layer on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin, wherein the protection layer comprises a lower conformal protection layer in the trench on the sidewalls of the fin and the surface of the first insulation layer and an upper protection layer on the lower conformal protection layer.
11. A Fin-Field Effect Transistor (Fin-FET) comprising:
an integrated circuit substrate having a fin and a trench defining the fin;
a first insulation layer in the trench such that a top surface of the first insulation layer is recessed beneath a top surface of the fin exposing sidewalls of the fin;
a protection layer on the first insulation layer;
a second insulation layer on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin;
a gate insulation layer on the fin and in the trench; and
a gate electrode on the gate insulation layer.
12. The Fin-FET of claim 1 , wherein a top surface of the protection layer is lower in level than the top surface of the fin.
13. The Fin-FET of claim 12 , wherein a top surface of the second insulation layer is recessed beneath the top surface of the fin.
14. The Fin-FET of claim 12 , wherein a top surface of the second insulation layer is higher than a top surface of the fin.
15. The Fin-FET of claim 1 , wherein a distance between the fin and the second insulating layer is shorter than a distance between the fin and the first insulating layer.