Computer readable mask shrink control processor

1. An apparatus comprising computer readable media comprising:

computer readable code for receiving a feature layout;

computer readable code for applying shrink correction on the feature layout, wherein the computer readable code for applying the shrink correction on the feature layout, comprises:

computer readable code for reducing dimensions of patterned layer lines of the patterned layer;

computer readable code for providing corner cutouts for forming features in a patterned layer;

computer readable code for generating a plurality of reticle layouts from the feature layout; and

computer readable code for applying shrink correction to the plurality of reticle layouts;

computer readable code for comparing a resulting test wafer with the feature layout and generating shrink correction rules based on the comparing; and

comprising computer readable code for applying the generated shrink correction rules to the feature layout.

2. A method, comprising:

receiving a feature layout;

performing a shrink connection on the feature layout to form a shrink corrected reticle layout, comprises:

generating a plurality of reticle layouts from the feature layout;

performing shrink correction on each of the plurality of reticle layouts; and

providing corner cutouts for forming features in a reticle;

forming a reticle based on the shrink corrected reticle layout, wherein the forming a patterned layer uses the reticle based on the shrink corrected reticle layout;

forming a patterned layer over a wafer based on the shrink corrected reticle layout, wherein the patterned layer has corner cutouts;

forming a sidewall layer over the patterned layer;

etching features into a substrate disposed below the patterned layer; and

comparing the etched features with the feature layout and generating shrink control rules based on the comparing the etched features with the feature layout.

3. The method, as recited in claim 2 , wherein the performing the shrink correction eliminates or minimizes use of OPC and wherein the performing the shrink correction eliminates the need for features to account for line edge shortening.

4. The method, as recited in claim 2 , wherein the comparing the sidewall layer formed over the patterned layer comprises etching features and comparing the etched features with the feature layout.

5. A semiconductor formed by the method as recited in claim 2 .