Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise non-planar partially depleted three-gated FETs having a greater channel width and a greater gate length and, thus, a greater drive current relative to the pass-gate and pull-up FETs. Additionally, for optimal electron mobility and hole mobility, respectively, the channels of the n-FETs and p-FETs can comprise semiconductors with different crystalline orientations.
1. A memory cell comprising:
a first non-planar transistor comprising:
a first semiconductor fin comprising a first channel; and
first gates adjacent said first channel;
a second non-planar transistor comprising:
a second semiconductor fin comprising a second channel; and
second gates adjacent said second channel; and
a third non-planar transistor comprising:
a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls; and
third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
wherein said third semiconductor fin is wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
2. The memory cell of claim 1 , wherein said third transistor has a predetermined channel width-to-gate length ratio that is sufficient to suppress short-channel effects and to provide an increased drive current relative to that of said first transistor and said second transistor.
3. The memory cell of claim 1 , wherein said first transistor and said second transistor comprise one of fully depleted fin-type field effect transistors and fully depleted trigate field effect transistors.
4. The memory cell of claim 1 , wherein said first channel and said third channel comprise a semiconductor material with a first crystalline orientation, and wherein said second channel comprises said semiconductor material with a second crystalline orientation.
5. The memory cell of claim 1 , further comprising one of a bulk wafer and a hybrid orientation wafer on which said first transistor, said second transistor and said third transistor are formed,
wherein said third transistor is a first-type transistor with a second-type semiconductor well below said third channel, and
wherein said second-type semiconductor well is adapted to receive an electrical bias so as to control a threshold voltage of said third transistor and further suppress said short-channel effects caused by said partially depleted third channel.
6. The memory cell of claim 1 , wherein said third channel is approximately 1.5 times wider than said first channel and said second channel.
7. A memory cell comprising:
a non-planar pass-gate transistor comprising:
a first semiconductor fin comprising a first channel; and
first gates adjacent said first channel;
a non-planar pull-up transistor comprising:
a second semiconductor fin comprising a second channel; and
second gates adjacent said second channel; and
a non-planar pull-down transistor comprising:
a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls; and
third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
wherein third semiconductor fin is wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
8. The memory cell of claim 7 , wherein said pull-down transistor has a predetermined channel width-to-gate length ratio that is sufficient to suppress short-channel effects and to provide an increased drive current relative to that of said pass-gate transistor and said pull-down transistor.
9. The memory cell of claim 7 , wherein said pass-gate transistor and said pull-up transistor comprise one of fully depleted fin-type field effect transistors and fully depleted trigate field effect transistors.
10. The memory cell of claim 7 , wherein said first channel and said third channel comprise a semiconductor material with a first crystalline orientation that is optimal for the mobility of electrons in an n-type transistor, and wherein said second channel comprises said semiconductor material with a second crystalline orientation that is optimal for the mobility of holes in a p-type transistor.
11. The memory cell of claim 7 , further comprising one of a bulk wafer and a hybrid orientation wafer on which said pass-gate transistor, said pull-up transistor and said pull- down transistor are formed,
wherein said pull-down transistor comprises an n-type transistor with a p-type semiconductor well below said third channel, and
wherein said p-type semiconductor well is adapted to receive an electrical bias so as to control a threshold voltage of said n-type transistor and to suppress short-channel effects.
12. The memory cell of claim 7 , wherein said third channel is approximately 1.5 times wider than said first channel and said second channel.
13. A memory cell comprising:
a non-planar pass-gate transistor comprising:
a first semiconductor fin comprising a first channel; and
first gates adjacent said first channel;
a non-planar pull-up transistor comprising:
a second semiconductor fin comprising a second channel; and
second gates adjacent said second channel; and
a non-planar pull-down transistor comprising:
a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls; and
third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
wherein third semiconductor fin is at least 1.5 times wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
14. The memory cell of claim 13 , wherein said pull-down transistor has a predetermined channel width-to-gate length ratio that is sufficient to suppress short-channel effects and to provide an increased drive current relative to that of said pass-gate transistor and said pull-down transistor.
15. The memory cell of claim 13 , wherein said pass-gate transistor and said pull-up transistor comprise one of fully depleted fin-type field effect transistors and fully depleted trigate field effect transistors.
16. The memory cell of claim 13 , wherein said first channel and said third channel comprise a semiconductor material with a first crystalline orientation that is optimal for the mobility of electrons in an n-type transistor, and wherein said second channel comprises said semiconductor material with a second crystalline orientation that is optimal for the mobility of holes in a p-type transistor.
17. The memory cell of claim 13 , further comprising one of a bulk wafer and a hybrid orientation wafer on which said pass-gate transistor, said pull-up transistor and said pull-down transistor are formed,
wherein said pull-down transistor comprises an n-type transistor with a p-type semiconductor well below said third channel, and
wherein said p-type semiconductor well is adapted to receive an electrical bias so as to control a threshold voltage of said n-type transistor and to suppress short-channel effects.