Power amplifier for amplifying high-frequency (H.F.) signals

1. A power amplifier for amplifying high frequency (HF) signals comprising:

several amplifier elements (T_ 1 , . . . , T_ 4 ) each with an amplifier channel (DS) and a gate terminal (G) for controlling the amplifier channel (DS), whereby the amplifier channels (DS) of the amplifier elements (T_ 1 , . . . , T_ 4 ) are connected in series;

a supply voltage (U_d) for the amplifier elements (T_ 1 , . . . , T_ 4 ) that is applied to the serial connection;

a selectable potential (U_g) that is present at the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection;

an HF input ( 2 ) that is connected to the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection via a first adjustment network ( 3 );

an HF output ( 5 ) that is connected to a drain (D) of the last amplifier element (T_ 4 ) of the serial connection via a second adjustment network ( 6 );

at least one capacitor (C_ 2 , . . . , C_ 4 ) connected to ground potential, each at the gate terminal (G) of the second amplifier element (T_ 2 ) and to the last amplifier element (T_ 4 ); and

at least one resistor (R_ 2 , . . . , R_ 4 ), each between the gate terminals (G) of adjacent amplifier elements (T_ 1 , T_ 2 ; T_ 2 , T_ 3 ; T_ 3 , T_ 4 ), at least one resistor (R_ 5 ) between the gate terminal (G) and the drain terminal (D) of the last amplifier element (T_ 4 ),

characterized by at least one limiting path ( 7 ) that is connected between the drain terminal (D) and the gate terminal (G) of at least one amplifier element of the serial connection from the first amplifier element (T_ 1 ) to the next to the last amplifier element (T_ 3 ), whereby the limiting path ( 7 ) can be toggled between a conducting state and a blocking state corresponding to a voltage (U — GD ) that is present between the drain terminal (D) and the gate terminal (G) of the amplifier elements (T_ 1 , . . . , T_ 3 ).

2. A power amplifier for amplifying high frequency (HF) signals comprising:

several amplifier elements (T_ 1 , . . . , T_ 4 ) each with an amplifier channel (DS) and a gate terminal (G) for controlling the amplifier channel (DS), whereby the amplifier channels (DS) of the amplifier elements (T_ 1 , . . . , T_ 4 ) are connected in series;

a supply voltage (U_d) for the amplifier elements (T_ 1 , . . . , T_ 4 ) that is applied to the serial connection;

a selectable potential (U_g) that is present at the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection;

an HF input ( 2 ) that is connected to the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection via a first adjustment network ( 3 );

an HF output ( 5 ) that is connected to a drain terminal (D) of the last amplifier element (T_ 4 ) of the serial connection via a second adjustment network ( 6 );

at least one capacitor (C_ 2 , . . . , C_ 4 ), whereby at the second amplifier element (T_ 2 ) and to the last amplifier element (T_ 4 ) of the serial connection, the gate terminals (G) are each connected to ground potential via one of the capacitors (C_ 2 , . . . , C_ 4 ); and

at least one resistor (R_ 2 , . . . , R_ 4 ), whereby one of the resistors (R_ 2 , . . . , R_ 4 ) each is connected between the gate terminals (G) of the amplifier elements (T_ 1 , T_ 2 ; T_ 2 , T_ 3 ; T_ 3 , T_ 4 ) that succeed each other in the serial connection, and at least one resistor (R_ 5 ) between the gate terminal (G) and the drain terminal (D) of the last amplifier element (T_ 4 ),

characterized in that the power amplifier comprises several transistor branches ( 10 , 11 , 12 ) connected to each other in parallel, where one branch ( 10 ) is an input branch and another branch ( 11 ) is an output branch, whereby

each of the branches ( 10 , 11 , 12 ) comprises several amplifier elements (T_ 1 , . . . , T_ 4 ), each with an amplifier channel (SD) and the gate terminal (G) for controlling the amplifier channel (SD), whereby the amplifier channels (SD) of the amplifier elements (T_ 1 , . . . , T_ 4 ) within a branch ( 10 ; 11 ; 12 ) are connected in series;

the power amplifier comprises an HF input ( 2 ) that is connected to the gate terminal (G) of the first amplifier elements (T_ 1 ) of the serial connection of the branches ( 10 , 11 , 12 ) via a first adjustment network ( 3 );

the power amplifier comprises an HF output ( 5 ) that is connected to the drain (D) of the last amplifier elements (T_ 4 ) of the serial connection of the branches ( 10 , 11 , 12 ) via a second adjustment network ( 6 );

each of the branches ( 10 , 11 , 12 ) comprises at least one capacitor (C_ 2 , . . . , C_ 4 ) connected to ground potential each at the gate terminal (G) of the second amplifier element (T_ 2 ) and to the last amplifier element (T_ 4 );

each of the branches ( 10 , 11 , 12 ) comprises at least one resistor (R_ 2 , . . . , R_ 4 ), each between the gate terminals (G) of adjacent amplifier elements (T_ 1 , T_ 2 ; T_ 2 , T_ 3 ; T_ 3 , T_ 4 ) and at least one resistor (R_ 5 ) between the gate terminal (G) and the drain terminal (D) of the last amplifier element (T_ 4 ); and

each of the branches ( 10 , 11 , 12 ) comprises at least one limiting path ( 7 ), that is connected between the drain terminal (D) and the gate terminal (G) of at least one of the amplifier elements of the serial connection of all branches ( 10 , 11 , 12 ) from the first amplifier element (T_ 1 ) to the next to the last amplifier element (T_ 3 ), whereby the limiting path ( 7 ) can be toggled between a conducting state and a blocking state corresponding to a voltage (U — GD ) that is present between the drain terminal (D) and the gate terminal (G) of the amplifier elements (T_ 1 , . . . , T_ 3 ).

3. A power amplifier as set forth in claim 1 , characterized in that a switching element ( 8 ) for toggling the limiting path ( 7 ) between the conducting state and the blocking state is located in the limiting path ( 7 ).

4. A power amplifier as set forth in claim 3 , characterized in that the switching element ( 8 ) is designed as a semiconductor switch (T_d).

5. A power amplifier as set forth in claim 4 , characterized in that the semiconductor switch (T_d) is designed as a diode.

6. A power amplifier as set forth in claim 4 , characterized in that the semiconductor switch (T_d) exhibits a switching path (DS) and a gate terminal (G) for switching the switching path (DS), whereby the gate terminal (G) is hot-wired to a drain terminal (D) of the semiconductor switch (T_d).

7. A power amplifier as set forth in one of the claim 1 , characterized in that a resistor element ( 9 ) is located in the limiting path ( 7 ).

8. A power amplifier as set forth in one of the claim 1 , characterized in that a limiting path ( 7 ) is connected only between the drain terminal (D) and the gate terminal (G) of the next to the last amplifier element (T_ 3 ) of the serial connection.

9. A power amplifier as set forth in one of the claim 1 , characterized in that a first limiting path ( 7 ′) is connected between the drain terminal (D) and the gate terminal (G) of the next to the last amplifier element (T_ 3 ) and an additional limiting path ( 7 ″) between the drain terminal (D) and the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection.

10. A power amplifier as set forth in one of the claim 1 , characterized in that from the first amplifier element (T_ 1 ) to the next to the last amplifier element (T_ 3 ) of the serial connection one limiting path ( 7 ′, 7 ″, 7 ′″) each is connected between the drain terminal (D) and the gate terminal (G).

11. A power amplifier as set forth in claim 2 , characterized in that with the exception of the output branch ( 11 ) at least one of the branches ( 10 ; 12 ) can be enabled or disabled corresponding to a desired output power of the power amplifier.

12. A power amplifier as set forth in claim 11 , characterized in that a switching element ( 13 ) is located between the first adjustment network ( 3 ) and the gate terminal (G) of the first amplifier element (T_ 1 ) of the at least one branch ( 10 ; 12 ), where said switching element can be actuated according to the desired output power of the power amplifier. 1

13. A power amplifier as set forth in one of the claim 1 , characterized in that the entire circuit of the power amplifier is designed in CMOS (Complementary Metal Oxide Semiconductor) technology.

14. A power amplifier as set forth in claim 2 , characterized in that a switching element ( 8 ) for toggling the limiting path ( 7 ) between the conducting state and the blocking state is located in the limiting path ( 7 ).

15. A power amplifier as set forth in claim 14 , characterized in that the switching element ( 8 ) is designed as a semiconductor switch (T_d).

16. A power amplifier as set forth in claim 15 , characterized in that the semiconductor switch (T_d) is designed as a diode.

17. A power amplifier as set forth in claim 15 , characterized in that the semiconductor switch (T_d) exhibits a switching path (DS) and a gate terminal (G) for switching the switching path (DS), whereby the gate terminal (G) is hot-wired to a drain terminal (D) of the semiconductor switch (T_d).

18. A power amplifier as set forth in one of the claim 2 , characterized in that a resistor element ( 9 ) is located in the limiting path ( 7 ).

19. A power amplifier as set forth in one of the claim 2 , characterized in that a limiting path ( 7 ) is connected only between the drain terminal (D) and the gate terminal (G) of the next to the last amplifier element (T_ 3 ) of the serial connection.

20. A power amplifier as set forth in one of the claim 2 , characterized in that a first limiting path ( 7 ′) is connected between the drain terminal (D) and the gate terminal (G) of the next to the last amplifier element (T_ 3 ) and an additional limiting path ( 7 ″) between the drain terminal (D) and the gate terminal (G) of the first amplifier element (T_ 1 ) of the serial connection.

21. A power amplifier as set forth in one of the claim 2 , characterized in that from the first amplifier element (T_ 1 ) to the next to the last amplifier element (T_ 3 ) of the serial connection one limiting path ( 7 ′, 7 ″, 7 ′″) each is connected between the drain terminal (D) and the gate terminal (G).

22. A power amplifier as set forth in one of the claim 2 , characterized in that the entire circuit of the power amplifier is designed in CMOS (Complementary Metal Oxide Semiconductor) technology.