IP Library › Granted Patent US 7,554,146
Granted Patent B2
US 7,554,146 · App. 11/317,859 · Granted Jun 30, 2009

Metal-insulator-metal capacitor and method of fabricating the same

Assignee: Samsung Electronics Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,554,146
App. No.
11/317,859
Granted
Jun 30, 2009
Kind
B2
Abstract

In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.

Claims (10)

1. A metal-insulator-metal (MIM) capacitor comprising:

a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect;

a dielectric layer on the lower electrode pattern;

a first upper electrode pattern on the dielectric layer;

an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface;

a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern;

a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer, wherein the second upper electrode comprises a barrier layer which is conformally formed along inner sidewalls and a bottom of the second upper electrode opening pattern and a conductive layer which is formed on the barrier layer to fill the second upper electrode opening pattern, wherein the barrier layer comprises a single layer of Ti or TiN or a double layer of Ti and TiN layers, and the conductive layer comprises tungsten (W); and

an upper interconnect on the interlayer insulating layer and contacts the second upper electrode, wherein the upper interconnect comprises aluminum.

2. The MIM capacitor of claim 1 , wherein the second upper electrode opening pattern exposes a portion of, or the entire, first upper electrode pattern.

3. The MIM capacitor of claim 1 , wherein the first upper electrode pattern comprises a Ti or TiN layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2006
From: WON, SEOK-JUN; KWON, DAE-JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017685/0700 →
Priority Claims (1)
KR 10-2004-0113210 · Dec 27, 2004 · national
Continuity (1)
Related Publication 20060157766A1 · Jul 20, 2006