Systems and methods for implementing reliability, availability and serviceability in a computer system
Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.
1. A method for implementing Reliability, Availability and Serviceability (RAS) in a computing system, comprising:
receiving at least one RAS event Management Interrupt (MI) signal to start a first MI period;
calculating the first MI period not to exceed a maximum period of Operating System (OS) code latency;
determining whether an RAS event associated with an MI signal is critical or non-critical;
executing at least one critical event during the first Management Interrupt (MI) period;
executing at least one non-critical event during the first MI period if time remains in the first MI period to execute the at least one non-critical event; and
scheduling a second MI period, subsequent to the first, to execute at least one non-critical event if a non-critical event is pending at the end of the first MI period.
2. The method of claim 1 , further comprising storing a queue of pending events classified as critical or non-critical.
3. The method of claim 1 , wherein calculating the first MI period not to exceed a maximum period of Operating System (OS) code latency comprises identifying a time limit for the MI period.
4. The method of claim 1 , further comprising classifying the copying of contents of one memory unit to another memory unit as a non-critical event.
5. The method of claim 1 , further comprising classifying an event of adding a memory unit to be accessed by a processor as a non-critical event.
6. The method of claim 1 , further comprising scheduling a critical event to be performed during a second MI period.
7. A system for implementing Reliability, Availability and Serviceability (RAS) in a computing system, comprising:
a Management Interrupt (MI) signal generator to generate an MI signal to signify that an RAS event is pending;
a memory to store an indicator to indicate whether a pending RAS event is critical or non-critical; and
a processor responsive to the MI signal to process critical events during the MI period initiated by the MI signal, to calculate the MI period not to exceed a maximum period of Operating System (OS) code latency, and to process non-critical events during the MI period if time exists during the MI period for processing the non-critical events.
8. The system of claim 7 , further comprising a timing mechanism to determine a time remaining in the MI period.
9. The system of claim 7 , further comprising a scheduler to schedule a subsequent MI period if time does not exist in the MI period for processing non-critical events.
10. The system of claim 7 , wherein the processor comprises a dispatcher to compute an exit time based upon an entry time and a maximum tolerable OS latency period to calculate the MI period not to exceed a maximum period of Operating System (OS) code latency.
11. The system of claim 7 , wherein a stored indicator is to indicate that copying contents of one memory unit to another memory unit is a non-critical event.
12. The system of claim 7 , wherein a stored indicator is to indicate that adding a memory unit to be accessed by a processor is a non-critical event.
13. The system of claim 7 , wherein a stored indicator is to indicate that replacing one processor with another is a critical event.
14. An article comprising a machine-readable storage medium that contains instructions, which when executed by a processor, cause said processor to perform operations for implementing Reliability, Availability and Serviceability (RAS) in a computing system, comprising:
receiving at least one RAS event Management Interrupt (MI) signal to start a first MI period;
calculating the first MI period not to exceed a maximum period of Operating System (OS) code latency;
determining whether an RAS event associated with an MI signal is critical or non-critical;
executing at least one critical event during the first Management Interrupt (MI) period;
executing at least one non-critical event during the first MI period if time remains in the first MI period to execute the at least one non-critical event; and
scheduling a second MI period, subsequent to the first, to execute at least one non-critical event if a non-critical event is pending at the end of the first MI period.
15. The machine readable storage medium of claim 14 , further comprising determining a time remaining in the first MI period to determine if time remains in the first MI period for processing non-critical events.
16. The machine readable storage medium of claim 14 , wherein calculating comprises specifying a latency period not to exceed a maximum period of Operating System (OS) code latency.
17. The machine readable storage medium of claim 14 , further comprising obtaining a current system time to subtract from the end time of the first MI period to determine a time remaining in the first MI period.
18. The machine readable storage medium of claim 14 , further comprising computing the first MI period end time as the sum of a current time of code entry plus a maximum tolerable OS latency period.
19. The machine readable storage medium of claim 14 , further comprising classifying an event of reducing a frequency of operation to reduce consumed power as a critical event.
20. The machine readable storage medium of claim 14 , further comprising classifying an event of adding a memory unit to be accessed by a processor as a non-critical event.