Semiconductor device and a method of manufacturing the same
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
1. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first interconnect over a semiconductor substrate;
(b) forming a first interlayer insulating film over the first interconnect:
(c) forming a first antireflective film over the first interlayer insulating film, and forming a first resist pattern over the first antireflective film;
(d) etching the first antireflective film and the first interlayer insulating film with the first resist pattern as a mask to form a first via hole in the first interlayer insulting film;
(e) removing the first resist pattern and the first antireflective film;
(f) filling a first filler inside of the first via hole;
(g) after the step (e), forming a second antireflective film over the first interlayer insulating film, and forming a second resist pattern over the second antireflective film;
(h) etching, with the second resist pattern as a mask, the first interlayer insulating film in a region including a region in which the first via hole has been formed, thereby forming a first interconnect trench in the first interlayer insulating film;
(i) removing the second resist pattern, the second antireflective film and the first filler;
(j) filling a first metal film in the first interconnect trench and in the first via hole, to form a second interconnect and a first connection portion together;
(k) forming a second interlayer insulating film over the second interconnect, wherein the second interlayer insulating film is divided by a first stopper film formed therein;
(l) forming a third antireflective film over the second interlayer insulating film, and forming a third resist pattern over the third antireflective film;
(m) etching the third antireflective film, the second interlayer insulating film and first stopper film with the third resist pattern as a mask to form a second via hole in the second interlayer insulting film;
(n) removing the third resist pattern and third antireflective film;
(o) filling a second filler inside of the second via hole;
(p) after the step (n), forming a fourth resist pattern over the second interlayer insulating film without using an antireflective film;
(q) etching, with the fourth resist pattern as a mask and with the first stopper film as an etching stopper, the second interlayer insulating film in a region including a region in which the second via hole has been formed, thereby forming a second interconnect trench in the second interlayer insulating film over the first stopper film;
(r) removing the fourth resist pattern and second filler; and
(s) filling a second metal film in the second interconnect trench and in the second via hole to form a third interconnect and a second connection portion together;
wherein a thickness of the second interlayer insulating film is larger than a thickness of the first interlayer insulating film,
wherein a depth of the second interconnect trench is deeper than a depth of the first interconnect trench,
wherein a diameter of the second via hole is greater than a diameter of the first via hole, and
wherein the first stopper film is made of a material having a lower optical reflectance than the second interlayer insulating film, whereby the first stopper film serves as an antireflective film when the fourth resist pattern is formed.
2. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film.
3. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the first interlayer insulating film is formed of an SiOC film as a main component.
4. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the second interlayer insulating film is formed of a silicon oxide film as a main component.
5. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the second interlayer insulating film is formed of a fluorinated silicon oxide film as a main component.
6. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the first stopper film is formed of an SiCN film.
7. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the first stopper film is formed of an SiN film or an SiON film.
8. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein a barrier insulating film for preventing diffusion of a metal of the first interconnect is formed between the first interconnect and the first interlayer insulating film.
9. A manufacturing method of a semiconductor integrated circuit device according to according to claim 8 ,
wherein the barrier insulating film is an SiCN film.
10. A manufacturing method of a semiconductor integrated circuit device according to claim 1 ,
wherein the metal film has copper as a main component.