Memory having bit line with resistor(s) between memory cells
For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
1. An integrated circuit comprising:
a memory array on the integrated circuit, the memory array having a bit line with one or more resistors along the bit line and having a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line, wherein at least one resistor along the bit line is between two locations at which memory cells are coupled to the bit line; and
access control circuitry on the integrated circuit to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell, wherein the access control circuitry includes resistance control circuitry to set a variable resistance of one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.
2. The integrated circuit of claim 1 , wherein a resistor along the bit line between two locations at which memory cells are coupled to the bit line includes one or more transistors.
3. The integrated circuit of claim 1 , wherein a resistor along the bit line between two locations at which memory cells are coupled to the bit line includes transistors coupled in parallel.
4. The integrated circuit of claim 1 , wherein a resistor along the bit line between two locations at which memory cells are coupled to the bit line includes one or more transistors having a gate fixedly coupled to a supply voltage node.
5. The integrated circuit of claim 1 , wherein the access control circuitry includes resistance control circuitry to selectively activate one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.
6. The integrated circuit of claim 5 , wherein the resistance control circuitry is to selectively activate one or more transistors of a resistor along the bit line between two locations at which memory cells are coupled to the bit line.
7. The integrated circuit of claim 1 , wherein the resistance control circuitry is to control a variable voltage applied to at least partially activate one or more transistors of a resistor along the bit line between two locations at which memory cells are coupled to the bit line.
8. The integrated circuit of claim 1 , wherein the plurality of memory cells include static random access memory cells.
9. The integrated circuit of claim 1 , wherein the memory array has a plurality of sections of memory cells coupled along the bit line and at least one resistor along the bit line between adjacent sections of memory cells.
10. A method comprising:
selecting a memory cell from a plurality of memory cells of a memory array having a bit line with one or more resistors along the bit line, the plurality of memory cells coupled to the bit line at a plurality of locations along the bit line wherein at least one resistor along the bit line is between two locations at which memory cells are coupled to the bit line;
setting a variable resistance of one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line; and
sensing a signal on the bit line from the selected memory cell.
11. The method of claim 10 , comprising:activating one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.
12. The method of claim 11 , wherein the activating includes using one or more supply voltage nodes fixedly coupled to a gate of one or more transistors of a resistor along the bit line between two locations at which memory cells are coupled to the bit line.
13. The method of claim 11 , wherein the activating includes selectively activating one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.
14. The method of claim 11 , wherein the activating includes selectively activating one or more transistors of a resistor along the bit line between two locations at which memory cells are coupled to the bit line.
15. The method of claim 10 , comprising:
controlling a variable voltage applied to at least partially activate one or more transistors of a resistor along the bit line between two locations at which memory cells are coupled to the bit line.
16. A system comprising:
volatile memory; and
a processor having cache memory including a memory array and access control circuitry, the memory array having a bit line with one or more resistors along the bit line and having a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line, wherein at least one resistor along the bit line is between two locations at which memory cells are coupled to the bit line, the access control circuitry to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell, wherein the access control circuitry includes resistance control circuitry to set a variable resistance of one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.
17. The system of claim 16 , wherein the access control circuitry includes resistance control circuitry to selectively activate one or more resistors along the bit line between two locations at which memory cells are coupled to the bit line.