IP Library Granted Patent US 7,560,780
Granted Patent B2
US 7,560,780 · App. 11/298,095 · Granted Jul 14, 2009

Active region spacer for semiconductor devices and method to form the same

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,560,780
App. No.
11/298,095
Granted
Jul 14, 2009
Kind
B2
Abstract

A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.

Claims (7)

1. A semiconductor device comprising:

a substrate having an isolation region adjacent to an active region, said isolation region having a top surface, a first portion of said active region having a top surface above a top surface of a second portion of said active region, and said top surface of said isolation region recessed below both said top surfaces of said first and second portions of said active region, forming a continuous sidewall of said first and second portions of said active region;

a spacer formed on said top surface of said isolation region and adjacent to said continuous sidewall of said first and second portions of said active region; and

a gate dielectric layer formed on a portion of said top surface of said second portion of said active region.

2. The device of claim 1 , wherein said spacer has a height and a width sufficient to seal off and protect said continuous sidewall of said first and second portions of said active region.

3. The device of claim 2 , wherein said spacer has a height substantially equal to the height of said continuous sidewall of said first and second portions of said active region, and a width of at least 20 Angstroms.

4. The device of claim 1 , wherein said spacer comprises a dielectric material selected from the group consisting of silicon dioxide, silicon nitride and silicon oxynitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2005
From: CURELLO, GIUSEPPE; POST, IAN R.; JAN, CHIA-HONG; TYAGI, SUNIT; BOHR, MARK
To: INTEL CORPORATION
Reel/Frame 017360/0199 →
Continuity (1)
Related Publication 20070132057A1 · Jun 14, 2007