Integrated circuit arrangement comprising at least one digital-analogue converter
The invention relates to an integrated circuit arrangement ( 10 ) comprising at least one digital-analogue converter ( 12 ) with a multitude of current-source transistors (N 1 -N 8 ) arranged parallel to each other for providing current components (I 1 -I 8 ) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N 1 -N 8 ) can be subjected to a shared adjustment potential by way of an adjustment potential line ( 14 ), which adjustment potential defines the individual current components (I 1 -I 8 ), and comprising an adjustment circuit ( 16 ) for providing the adjustment potential at the adjustment potential line ( 14 ). In order to drastically reduce interference, in particular noise, in the individual current components (I 1 -I 8 ), the integrated circuit arrangement ( 10 ) comprises an external connection ( 18 ), which is connected to the adjustment potential line ( 14 ) for connecting an external capacitor (C 0 ).
1. An integrated circuit arrangement comprising at least one digital-analogue converter ( 12 ) with a multitude of current-source transistors (N 1 -N 8 ) arranged parallel to each other for providing current components (I 1 -I 8 ) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N 1 -N 8 ) can be subjected to a shared adjustment potential by way of an adjustment potential line ( 14 ), which adjustment potential defines the individual current components (I 1 -I 8 ), and comprising an adjustment circuit ( 16 ) for providing the adjustment potential at the adjustment potential line ( 14 ), characterised in that the integrated circuit arrangement comprises an external connection ( 18 ), which is connected to the adjustment potential line ( 14 ), for connecting an external capacitor (C 0 ).
2. The integrated circuit arrangement according to claim 1 , comprising a further external connection ( 20 ) that is connected to a reference potential line ( 22 ) of the integrated circuit arrangement.
3. The integrated circuit arrangement according to claim 1 , wherein in a section of the adjustment potential line ( 14 ), which section leads from the adjustment circuit ( 16 ) to the multitude of current-source transistors (N 1 -N 8 ), a resistor element (R 0 ) is arranged.
4. The integrated circuit arrangement according to claim 1 , comprising a multitude of digital-analogue converters (DAC 1 -DAC 4 ) each comprising a multitude of current-source transistors (N 1 -N 8 ), wherein the adjustment circuit ( 16 ) and the adjustment potential line ( 14 ) are provided to be shared by the multitude of digital-analogue converters (DAC 1 -DAC 4 ).
5. The integrated circuit arrangement according to claim 1 , wherein the digital-analogue converter ( 12 ; DAC 1 -DAC 4 ) is arranged in a feedback arrangement of a delta-sigma analogue-digital converter (ADC 1 -ADC 4 ) formed by the integrated circuit.
6. The integrated circuit arrangement according to claim 1 , comprising a multitude of delta-sigma analogue-digital converters (ADC 1 -ADC 4 ), in each case comprising at least one digital-analogue converter (DAC 1 -DAC 4 ) in a feedback arrangement of the delta-sigma analogue-digital converter (ADC 1 -ADC 4 ), wherein the adjustment circuit ( 16 ) and the adjustment potential line ( 14 ) are provided to be shared by the multitude of digital-analogue converters (DAC 1 -DAC 4 ).
7. The integrated circuit arrangement according to claim 6 , wherein the multitude of delta-sigma analogue-digital converters (ADC 1 -ADC 4 ) are provided for redundant analogue-digital conversion of a shared analogue input signal (Vin), and digital output signals (OUT 1 -OUT 4 ) of the individual delta-sigma analogue-digital converters (ADC 1 -ADC 4 ) are fed to a digital signal processing device ( 24 ) of the integrated circuit arrangement.
8. A method of using an integrated circuit arrangement according to claim 5 comprising the step of converting an analogue measuring signal (Vin) to a digital signal by use of said integrated circuit arrangement.