IP Library › Granted Patent US 7,561,095
Granted Patent B2
US 7,561,095 · App. 11/889,698 · Granted Jul 14, 2009

Pipelined analog-to-digital converter having interleaved sample-and-hold circuits coupled in common

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,561,095
App. No.
11/889,698
Granted
Jul 14, 2009
Kind
B2
Abstract

A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.

Claims (23)

1. An analog front end LSI for a camera comprising:

a pipelined A-D conversion circuit which has a plurality of stages and is coupled in series with an input terminal to which an analog signal to be converted is inputted, the input terminal being connected to receive the analog signal from an image sensor of a camera;

wherein the stages other than at least one stage, coupled to the input terminal through the one stage, respectively have two or more sample and hold circuits and an amplifier coupled in common with the two or more sample and hold circuits, and the two or more sample and hold circuits perform interleave operations;

wherein the stages comprise: a sub-A-D converter that carries out A-D conversion to convert an analog signal into a digital signal of a small number of bits; a sub-D-A converter that converts from the digital output signal of the sub-A-D converter to analog; a subtracter that generates a signal indicating the difference between the analog output signal of the sub-D-A converter and the analog signal to be converted; and an amplifier that amplifies, samples, and holds the output signal of the subtracter,

wherein the sample and hold circuits comprise the sub-D-A converter and the subtracter; and

wherein the stages in which the interleave operation is performed comprise two or more sample and hold circuits and two or more sub-A-D converters, and the sample and hold circuits and the sub-A-D converters perform synchronous operations.

2. The analog front end LSI for a camera according to claim 1 ,

wherein the amplifier comprises an input terminal 1 and an input terminal 2 ,

wherein, when a sampling operation is performed for a signal inputted to the input terminal 1 , a holding operation is performed for a signal inputted to the input terminal 2 , and

wherein, when a holding operation is performed for a signal inputted to the input terminal 1 , a sampling operation is performed for a signal inputted to the input terminal 2 .

3. The analog front end LSI for a camera according to claim 2 ,

wherein the sampling operation and the holding operation are performed in synchronization with the interleave operation.

4. The analog front end LSI for a camera according to claim 3 ,

wherein the sub-D-A converter and the amplifier that performs the sampling operation and holding operation form an integral circuit synthesized using switched capacitors.

5. The analog front end LSI for a camera according to claim 4 , further comprising:

a correlated double sampling circuit that has a sample and hold circuit receiving the feed through portion of a pixel signal formed by a solid-state image sensing device, and receives the signal portion that represents the difference from the feed through portion;

a logic circuit that receives the output signal of the pipelined A-D conversion circuit and feeds a black level clamp signal back to the correlation double sampling circuit; and

a programmable gain amplifier that receives the output signal of the pipelined A-D conversion circuit and amplifies the output signal by a factor of appropriate gain,

wherein the output of the correlation double sampling circuit is inputted to the pipelined A-D converter.

6. An analog front end LSI for a camera comprising:

a pipelined A-D conversion circuit which has a plurality of stages and is coupled in series with an input terminal to which an analog signal to be converted is inputted,

wherein the stages respectively have two or more sample and hold circuits, two or more sub-A-D converts, and an amplifier coupled in common with the two or more sample and hold circuits, and

wherein the two or more sub-A-D converters perform interleave operations.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 29, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024755/0338 →
Priority Claims (1)
JP 2004-255299 · Sep 2, 2004 · national
Continuity (2)
Continuation 1119758600 · Aug 5, 2005
Related Publication 20080174465A1 · Jul 24, 2008