Performance and area scalable cell architecture technology
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
1. An integrated circuit, comprising:
an area having a layout aligned in rows, wherein each row is definable by a pair of row boundaries;
a plurality of cells, comprising a first set of cells, wherein each cell in the first set of cells spans at least two rows and comprises:
a PMOS transistor having a first source/drain region and a second source/drain region that both span across a first one of the row boundaries; and
an NMOS transistor having a first source/drain region and a second source/drain region that both span across a second one of the row boundaries.
2. The integrated circuit of claim 1 wherein each cell in the first set of cells spans at least three rows.
3. The integrated circuit of claim 1 wherein each cell in the first set of cells spans comprises:
a first area extending from a first row boundary toward the source/drain region of the PMOS transistor;
a second area extending from a second row boundary toward the source/drain region of the NMOS transistor; and
circuitry located in the first and second area.
4. The integrated circuit of claim 3 wherein the circuitry located in the first and second area is selected from a set consisting of an additional transistor that is smaller than the NMOS transistor and the PMOS transistor, a decoupling capacitor, a diffusion antenna protection device, and a failure analysis target.
5. The integrated circuit of claim 1 wherein the plurality of cells further comprises a second set of cells, wherein each cell in the second set of cells spans one row.
6. The integrated circuit of claim 1 wherein the plurality of cells further comprises a second set of cells, wherein each cell in the second set of cells spans two rows.
7. The integrated circuit of claim 6 wherein each cell in the second set of cells comprises:
a first transistor of a first conductivity type; and
a second transistor of a second conductivity type, wherein a source/drain region of one of the first and second transistor comprises two physically separated regions.
8. The integrated circuit of claim 6 wherein each cell in the first set of cells spans at least three rows.
9. The integrated circuit of claim 1 :
wherein the plurality of cells further comprises a second set of cells, wherein each cell in the second set of cells spans one row; and
wherein the plurality of cells further comprises a third set of cells, wherein each cell in the third set of cells spans two rows.
10. The integrated circuit of claim 9 and further comprising a power conductor spanning in a single dimension, parallel to a row in the rows, across a cell in the first set, a cell in the second set, and a cell in the third set.
11. The integrated circuit of claim 1 wherein the first source/drain region of the PMOS transistor is oriented relative to the first source/ drain region of the NMOS transistor such that an imaginary line perpendicular to the first and second ones of the row boundaries passes through the first source/drain region of the PMOS transistor and the first source/drain region of the NMOS transistor.