Method for forming semiconductor device having fin structure
A method for forming a semiconductor device having a fin structure includes (a) forming a device isolation film over a silicon substrate to define an active area, (b) etching silicon substrate of gate forming region to form a trench, (c) selectively etching the device isolation film of a trench boundary, (d) forming a gate oxide film over the entire surface of the resulting structure, (e) depositing an electrode material over the entire surface of the resulting structure to form a gate electrode, and (f) forming a gate spacer over a sidewall of the gate electrode.
1. A method for forming a semiconductor device having a fin structure, the method comprising:
(a) forming a device isolation film over a silicon substrate to define an active area, wherein the device isolation film has a double oxide film structure comprising a first oxide film and a second oxide film;
(b) etching the silicon substrate of a gate forming region of the active area to form a trench;
(c) selectively etching the device isolation film of a boundary of the trench, wherein the device isolation film is etched by wet-etching the first oxide film and the second oxide film, a wet-etching speed of the first oxide film being faster than a wet-etching speed of the second oxide film such that a saddle fin structure is formed;
(d) forming a gate oxide film over the entire surface of the resulting structure;
(e) depositing an electrode material over the entire surface of the resulting structure to form a gate electrode; and
(f) forming a gate spacer over a sidewall of the gate electrode.
2. The method according to claim 1 , wherein the thickness of the first oxide film and the second oxide film ranges from 300 to 3000 Å.
3. The method according to claim 1 , wherein the first oxide film includes a SOD oxide film, and the second oxide film includes a HDP oxide film.
4. The method according to claim 1 , wherein the etching of step (b) is a dry-etching process that is performed to a depth ranging from 300 to 3000 Å.
5. The method according to claim 1 , wherein the bottom of the trench has a square or round shape.
6. The method according to claim 1 , wherein the etching of step (c) is a wet-etching process performed to etch the first oxide film to remove a thickness ranging from 100 to 1000 Å and to etch the second oxide film to remove a thickness ranging from 20 to 150 Å.
7. The method according to claim 1 , wherein the etching of step (c) is selectively performed depending on an etching speed difference between the first oxide film and the second oxide film.
8. The method according to claim 1 , wherein the etching of step (c) is performed in a BOB or HF solution.
9. The method according to claim 1 , wherein the thickness of the gate oxide film ranges from 30 to 300 Å.
10. The method according to claim 1 further comprising forming a selective thermal oxide film after step (e).
11. The method according to claim 10 , wherein the selective thermal oxide film is formed over the sidewall of polysilicon layer and over the silicon substrate.
12. The method according to claim 10 , wherein the thickness of the selective thermal oxide film ranges from 20 to 200 Å.