Transistors with stressed channels
View Patent ↗A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.
1. A semiconductor structure comprising:
a substrate;
a gate over the substrate;
a channel region in the substrate and directly underlying the gate;
a non-silicide region of the substrate not directly underlying the gate, wherein the non-silicide region adjoins the channel region;
a source/drain region comprising a recess in the substrate, wherein the source/drain region comprises:
a first source/drain extension region;
a second source/drain extension region further from the gate than the first source/drain extension region; and
a deep source/drain region further from the gate than the second source/drain extension region; and
a silicide region on the source/drain region, wherein the silicide region has a top surface comprising a lower portion, and a higher portion between the lower portion and the non-silicide region, the lower portion having a top surface lower than a top surface of the higher portion by a step height, wherein a width of the non-silicide region and the step height have a ratio of less than or equal to about 3.
2. The semiconductor structure of claim 1 , wherein the width of the non-silicide region and the step height have a ratio of between about 0.5 and about 2.
3. The semiconductor structure of claim 1 , wherein the step height is greater than about 20 nm.
4. The semiconductor structure of claim 1 , wherein the lower portion of the top surface of the silicide region has a spacing from a respective edge of the non-silicide region, and wherein the step height and the spacing have a ratio of less than or equal to about 3.
5. The semiconductor structure of claim 4 , wherein the width of the non-silicide region is between about 10 nm and about 100 nm.
6. The semiconductor structure of claim 1 , wherein the first source/drain extension region has a first depth, and wherein the first depth and the step height have a ratio of less than or equal to about 0.8.
7. The semiconductor structure of claim 1 , wherein the second source/drain extension region has a second depth, and wherein the second depth and the step height have a ratio of between about 1 and about 2.
8. The semiconductor structure of claim 1 , wherein the deep source/drain region has a third depth, and wherein the third depth and the step height have a ratio of between about 1.5 and about 5.
9. The semiconductor structure of claim 1 further comprising a tensile-stressed layer over the gate, the non-silicide region, and the source/drain region, wherein the tensile-stressed layer contacts the lower portion of the top surface of the silicide region.
10. The semiconductor structure of claim 1 , wherein the higher portion of the top surface of the silicide region is substantially flat with a respective portion of the silicide region having a substantially uniform thickness, and wherein the silicide region further comprises a substantially vertical portion between and adjoining the higher portion and the lower portion.
11. A semiconductor structure comprising:
a substrate;
a gate over the substrate;
a non-silicide region of the substrate adjacent the gate;
a source/drain region comprising:
a recess in the substrate;
a first source/drain extension region;
a second source/drain extension region further from the gate than the first source/drain extension region; and
a deep source/drain region having a depth; and
a silicide region on the source/drain region, wherein the silicide region has a top surface comprising:
a lower portion; and
a higher portion between the lower portion and the non-silicide region, the lower portion having a top surface lower than a top surface of the higher portion by a step height, wherein a width of the non-silicide region and the step height have a ratio of less than or equal to about 3, and wherein the depth and the step height have a ratio of between about 1.5 and about 5.
12. The semiconductor structure of claim 11 , wherein the higher portion of the top surface of the silicide region is substantially flat with a respective portion of the silicide region having a substantially uniform thickness, and wherein the silicide region further comprises a substantially vertical portion between and adjoining the higher portion and the lower portion.
13. The semiconductor structure of claim 11 , wherein the deep source/drain region is further from the gate than the second source/drain extension region.
14. The semiconductor structure of claim 11 , further comprising a tensile-stressed layer over the gate, the non-silicide region, and the source/drain region, wherein the tensile-stressed layer contacts a portion of the lower portion of the top surface of the silicide region.