Circuit to reduce internal ESD stress on device having multiple power supply domains
An ESD protection circuit is designed on an integrated circuit ( 100 ) having a first power supply bus ( 106 ) and a second power supply bus ( 108 ). The circuit includes a first logic gate ( 116, 118 ) having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate ( 122, 124 ) has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device ( 306 ) is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.
1. A circuit, comprising:
a first power supply bus;
a first reference bus;
a second power supply bus;
a second reference bus;
a first logic gate having a current path coupled between the first power supply bus and the first reference bus, the first logic gate having a first terminal;
a second logic gate having a current path coupled between the second power supply bus and the second reference bus, the second logic gate having a second terminal;
a first transistor of a first conductivity type having a current path coupled between the first and second terminals and having a gate coupled to the first power supply bus;
a second transistor of a second conductivity type having a current path coupled between the first and second terminals and having a gate coupled to the first reference bus; and
a first device coupled in series with the current path of the second logic gate, the first device being always on during normal circuit operation.
2. A circuit as in claim 1 , comprising a second device coupled in series with the current path of the first logic gate, the second device being always on during normal circuit operation.
3. A circuit as in claim 1 , comprising a second device coupled in series with the current path of the second logic gate, the second device being always on during normal circuit operation.
4. A circuit as in claim 3 , wherein the second logic gate is a CMOS logic gate having a P-channel transistor and an N-channel transistor connected in series, and wherein the first device is connected to a source of the N-channel transistor and the second device is connected to a source of the P-channel transistor.
5. A circuit as in claim 3 , wherein the second logic gate is a CMOS logic gate having a P-channel transistor and an N-channel transistor connected in series, and wherein the first device is connected to a drain of the N-channel transistor and the second device is connected to a drain of the P-channel transistor.
6. A circuit as in claim 1 , wherein the first reference bus is coupled to the second reference bus by anti parallel diodes.
7. A circuit as in claim 1 , wherein the first reference bus is coupled to the second reference bus by external power supply terminals.
8. A circuit, comprising:
a first power supply bus;
a first reference bus;
a second power supply bus;
a second reference bus;
a first logic gate having a current path coupled between the first power supply bus and the first reference bus, the first logic gate having an output terminal;
a second logic gate having a current path coupled between the second power supply bus and the second reference bus, the second logic gate having an input terminal;
a first transistor of a first conductivity type having a current path coupled between the output and input terminals and having a gate coupled to the first power supply bus;
a second transistor of a second conductivity type having a current path coupled between the output and input terminals and having a gate coupled to the first reference bus; and
a first device coupled in series with the current path of the first logic gate, the first device being always on during normal circuit operation.
9. A circuit as in claim 8 , comprising a second device coupled in series with the current path of the first logic gate, the second device being always on during normal circuit operation.
10. A circuit as in claim 9 , wherein the first logic gate is a CMOS logic gate having a P-channel transistor and an N-channel transistor connected in series, and wherein the first device is connected to a source of the N-channel transistor and the second device is connected to a source of the P-channel transistor.
11. A circuit as in claim 9 , wherein the second logic gate is a CMOS logic gate having a P-channel transistor and an N-channel transistor connected in series, and wherein the first device is connected to a drain of the N-channel transistor and the second device is connected to a drain of the P-channel transistor.
12. A circuit as in claim 8 , wherein the first power supply bus is coupled to the second power supply bus by anti parallel diodes.
13. A circuit as in claim 8 , wherein the first power supply bus is coupled to the second power supply bus by external power supply terminals.