Routing engine, method of routing a test probe and testing system employing the same

1. A routing engine for use with a test unit having at least one test probe, comprising:

an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit; and

a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.

2. The engine as recited in claim 1 wherein a mode for analyzing the alternative test probe routing sequences is selected from the group consisting of:

a real-time analysis mode; and

an offline analysis mode.

3. The engine as recited in claim 1 wherein the alternative test probe routing sequences are based on a semiconductor wafer mapping of the representative circuit chips that employs one selected from the group consisting of:

a nearest neighbor approach;

a greedy path approach; and

a Lin-Kernighan approach.

4. The engine as recited in claim 1 wherein each of the representative circuit chips corresponds to a sample chosen from a grid-cell area of N circuit chips by M circuit chips on the semiconductor wafer.

5. The engine as recited in claim 4 wherein the grid-cell area corresponds to three circuit chips by four circuit chips.

6. The engine as recited in claim 1 wherein the test probe path is a set of test probe routing subsequences that respectively correspond to a set of different test areas on the semiconductor wafer.

7. The engine as recited in claim 1 wherein the test probe path is hierarchal and employs first-pass and second-pass test probe routing sequences.

8. The engine as recited in claim 7 wherein the second-pass test probe routing sequence provides at least one perimeter-defining test probe path that determines a defective area on the semiconductor wafer.

9. A method of routing a test probe for use with a semiconductor wafer, comprising:

analyzing alternative test probe routing sequences that employ representative circuit chips of the semiconductor wafer to be tested by the test probe;

selecting at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path; and guiding the test probe along the test probe path.

10. The method as recited in claim 9 wherein a mode for analyzing the alternative test probe routing sequences is selected from the group consisting of:

a real-time analysis mode; and

an offline analysis mode.

11. The method as recited in claim 9 wherein the alternative test probe routing sequences are based on a semiconductor wafer mapping of the representative circuit chips that employs one selected from the group consisting of:

a nearest neighbor approach;

a greedy path approach; and

a Lin-Kernighan approach.

12. The method as recited in claim 9 wherein each of the representative circuit chips corresponds to a sample chosen from a grid-cell area of N circuit chips by M circuit chips on the semiconductor wafer.

13. The method as recited in claim 12 wherein the grid-cell area corresponds to three circuit chips by four circuit chips.

14. The method as recited in claim 9 wherein the test probe path is a set of test probe routing subsequences that respectively correspond to a set of different test areas on the semiconductor wafer.

15. The method as recited in claim 9 wherein the test probe path is hierarchal and employs first-pass and second-pass test probe routing sequences.

16. The method as recited in claim 15 wherein the second-pass test probe routing sequence provides at least one perimeter-defining test probe path that determines a defective area on the semiconductor wafer.

17. A testing system; comprising:

a test unit having at least one test probe;

a routing engine coupled to the test unit, including:

an analysis unit that analyzes alternative test probe routing sequences by employing representative circuit chips of a semiconductor wafer to be tested by the test unit, and

a selection unit that selects at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path; and

a controller that is coupled to the routing engine and guides the test probe along the test probe path.

18. The system as recited in claim 17 wherein a mode for analyzing the alternative test probe routing sequences is selected from the group consisting of:

a real-time analysis mode; and

an offline analysis mode.

19. The system as recited in claim 17 wherein the alternative test probe routing sequences are based on a semiconductor wafer mapping of the representative circuit chips that employs one selected from the group consisting of:

a nearest neighbor approach;

a greedy path approach; and

a Lin-Kernighan approach.

20. The system as recited in claim 17 wherein each of the representative circuit chips corresponds to a sample chosen from a grid-cell area of N circuit chips by M circuit chips on the semiconductor wafer.

21. The system as recited in claim 20 wherein the grid-cell area corresponds to three circuit chips by four circuit chips.

22. The system as recited in claim 17 wherein the test probe path is a set of test probe routing subsequences that respectively correspond to a set of different test areas on the semiconductor wafer.

23. The system as recited in claim 17 wherein the test probe path is hierarchal and employs first-pass and second-pass test probe routing sequences.

24. The system as recited in claim 23 wherein the second-pass test probe routing sequence provides at least one perimeter-defining test probe path that determines a defective area on the semiconductor wafer.