IP Library Granted Patent US 7,605,070
Granted Patent B2
US 7,605,070 · App. 11/154,474 · Granted Oct 20, 2009

Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same

Assignee: Hynix Semiconductor, Inc.
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Quick Facts
Patent No.
US 7,605,070
App. No.
11/154,474
Granted
Oct 20, 2009
Kind
B2
Abstract

Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal layer on the epitaxial stack. Accordingly, in accordance with the present invention, the contact plug is selectively doped in a high concentration, thereby reducing a contact resistance. Furthermore, the present invention also provides an effect of reducing degradation in a device property without decreasing yields of products by minimizing a thermal budget through using a SEG-silicon germanium layer capable of obtaining a high doping concentration and a high deposition speed.

Claims (27)

1. A method for fabricating a semiconductor device comprising the steps of:

forming a plurality of gate patterns directly on a substrate;

filling the space between the gate patterns by forming an inter-layer insulation layer on the substrate;

forming a contact hole, which exposes a predetermined surface of the substrate between the gate patterns, by selectively etching the inter-layer insulation layer;

performing a first pre-cleaning process to recover a defect on a bottom portion of the contact hole and remove a first natural oxide layer;

forming a sacrificial layer at a temperature, where an amorphous structure is formed, to remove a fine oxide layer remaining on a surface of the substrate of the bottom portion of the contact hole after performing the first pre-cleaning process;

removing the sacrificial layer;

forming an epitaxial stack including at least a SEG-silicon germanium layer through the SEG process on the contact hole;

performing a second pre-cleaning process to remove a second natural oxide layer on a surface of the epitaxial stack; and

forming a metal layer filling the contact hole on the epitaxial stack,

wherein a surface of the metal layer is formed on a same plane as a surface of the gate patterns.

2. The method of claim 1 , wherein the step of forming the epitaxial stack includes the steps of:

growing a first SEG-silicon layer;

growing a SEG-silicon germanium layer on the first SEG-silicon layer; and

growing a second SEG-silicon layer on the SEG-silicon germanium layer.

3. The method of claim 2 , wherein the step of growing the SEG-silicon germanium layer includes the steps of:

growing the first SEG-silicon layer to a predetermined thickness; and

additionally flowing a germane (GeH 4 ) gas, thereby adding a germanium (Ge) gas with a content ratio ranging from approximately 5% to approximately 30% to the SEG-silicon germanium layer.

4. The method of claim 2 , wherein during growing the first SEG-silicon layer, the SEG-silicon germanium layer and the second SEG-silicon layer, P is doped through an in-situ process.

5. The method of claim 4 , wherein a doping concentration of P ranges from approximately 1×10 19 atoms/cm 3 to approximately 5×10 19 atoms/cm 3 for the first and the second SEG-silicon layers and a doping concentration of P ranges from approximately 8×10 19 atoms/cm 3 to approximately 1×10 20 atoms/cm 3 for the SEG-silicon germanium layer.

6. The method of claim 2 , wherein the first and the second SEG-silicon layers are grown to a thickness ranging from approximately 10 Å to approximately 50 Å and the SEG-silicon germanium layer is grown in a thickness ranging from approximately 100 Å to approximately 300 Å.

7. The method of claim 1 , wherein the steps of forming the sacrificial layer, removing the sacrificial layer and growing the epitaxial stack are performed by using an apparatus selected from a group consisting of a low pressure chemical vapor deposition (LPCVD) apparatus, a very low pressure chemical vapor deposition (VLPCVD) apparatus, a plasma enhanced chemical vapor deposition (PECVD) apparatus, an ultra high vacuum chemical vapor deposition (UHVCVD) apparatus, a rapid thermal chemical vapor deposition (RTCVD) apparatus and an atmospheric pressure chemical vapor deposition (APCVD) apparatus at a temperature ranging from approximately 400° C. to approximately 700° C.

8. The method of claim 1 , wherein for the step of forming the sacrificial layer, silicon, selectively doped with impurities ranging from approximately 1×10 20 atoms/cm 3 to approximately 1×10 21 atoms/cm 3 at a temperature ranging from approximately 500° C. to approximately 600° C., is deposited in a thickness ranging from approximately so 50 Å to approximately 80 Å.

9. The method of claim 1 , wherein the step of removing the sacrificial layer is performed in a chamber where the sacrificial layer is formed by using a halogen gas through an in-situ process.

10. The method of claim 1 , wherein the metal layer is selected from a group consisting of titanium (Ti), titanium nitride (TiN), nickel (Ni), tungsten (W) and cobalt (Co).

11. The method of claim 1 , wherein the first and the second pre-cleaning processes are employed through one of a dry cleaning process and a wet cleaning process.

12. The method of claim 11 , wherein the dry cleaning process is performed through a rapid thermal process in one of a hydrogen gas atmosphere and a hydrogen based gas atmosphere at a high temperature ranging from approximately 700° C. to approximately 900° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2005
From: LEE, YOUNG-HO
To: HYNIX SEMICONDUCTOR, INC.
Reel/Frame 016702/0078 →
Priority Claims (1)
KR 10-2005-0033263 · Apr 21, 2005 · national
Continuity (1)
Related Publication 20060240655A1 · Oct 26, 2006