Dynamic clock switch mechanism for memories to improve performance
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation will occur. The dynamic extension of the clock signal includes delaying the clock signal, forming a waveform toggling between states upon each predetermined state transition of the delayed clock signal, selecting the clock signal when this waveform has a first stage, and selecting the delayed clock signal when this waveform has a second state. Dynamic extension is prevented during a test mode. An apparatus of this invention uses a flip-flop and a multiplexer to produce the dynamically delayed clock.
1. A data processing apparatus comprising:
a delay having an input receiving a system clock signal and an output producing a delayed clock signal delayed by a predetermined amount;
a flip-flop having a clock input receiving said delayed clock signal, an enable input receiving a signal indicative of whether a cache fill operation will occur in a next cycle and an output;
an AND gate having a first input receiving said output of said flip-flop, a second input receiving a signal indicative of whether a test mode is active in the data processing apparatus and an output;
said signal indicative of whether a test mode is active having a polarity whereby said multiplexer selected said system clock signal whenever said test mode is active;
a multiplexer having a first input receiving said delayed clock signal, a second input receiving said system clock signal, a control input connected to said output of said AND gate and an output, said output corresponding to one of said inputs dependent upon a digital state of said control input; and
a cache memory receiving said output of said multiplexer at a clock input.
2. A data processing apparatus comprising:
a delay having an input receiving a system clock signal and an output producing a delayed clock signal delayed by a predetermined amount;
a flip-flop having a clock input receiving said delayed clock signal, an enable input receiving a signal indicative of whether a cache fill operation will occur in a next cycle and an output;
a multiplexer having a first input receiving said delayed clock signal, a second input receiving said system clock signal, a control input connected to said output of said flip-flop and an output, said output corresponding to one of said inputs dependent upon a digital state of said control input;
a cache memory receiving said output of said multiplexer at a clock input; and
a cache miss register storing recalled data from a cache fill operation for supply to a requesting central processing unit, said cache miss register receiving said delayed clock signal at a clock input.