Fully isolated photodiode stack
An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
1. An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells, the color imager cell array comprising:
a bulk silicon (Si) substrate;
a single layer of epitaxial Si overlying the substrate, including a plurality of color imager cells, where each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure; and,
a U-shaped well liner, fully isolating each photodiode set from adjacent photodiode sets in the array.
2. The color imager cell array of claim 1 wherein each photodiode includes a doped Si layer physically interfacing the well liner.
3. The color imager cell array of claim 2 wherein the well liner includes a first wall physically interfacing a doped Si layer of each photodiode in the photodiode set.
4. The color imager cell array of claim 3 wherein each photodiode includes a p doped Si layer physically interfacing the first wall; and,
wherein the well liner is p doped and electrically connected to a reference voltage.
5. The color imager cell array of claim 4 wherein the well liner includes a well bottom physically interfacing the first wall; and,
wherein the third, bottom-most, photodiode includes a p doped layer that is part of the well bottom.
6. The color imager cell array of claim 5 wherein the first photodiode includes a first doped Si layer formed in a top surface region, and an underlying first p doped Si layer physically interfacing the first wall;
wherein the second photodiode includes a second doped Si layer underlying the first p doped Si layer, an underlying second p doped Si layer physically interfacing the first wall, and an n doped first vertical structure physically interfacing the second doped Si layer to a top surface region; and,
wherein the third photodiode includes a third doped Si layer underlying the second p doped Si layer, an underlying third p doped Si layer physically interfacing the first wall and forming a portion of the well bottom, and an n doped second vertical structure physically interfacing the third doped Si layer to a top surface region.
7. The color imager cell array of claim 6 wherein the well liner includes a p doped second wall physically interfacing the second vertical structure, the third doped Si layer, and the well bottom.
8. The color imager cell array of claim 7 wherein the first, second, and third doped Si layers are n doped.
9. The color imager cell array of claim 6 wherein the first doped Si layer is n doped, and the second and third Si layers are p doped.
10. The color imager cell array of claim 6 further comprising:
isolating structures separating the first and second vertical structures, and separating the first vertical structure and the first doped Si layer, the isolating structures selected from a group consisting of dielectric material, p doped Si, and combinations of dielectric material and p doped Si.
11. The color imager cell array of claim 1 wherein the photodiode set multi-junction structure is formed in the Si substrate.
12. A method for forming an array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells, the method comprising:
providing a bulk silicon (Si) substrate;
forming a layer of epitaxial Si overlying the substrate;
forming a plurality of color imager cells, where each color imager cell includes a photodiode set formed in the epitaxial Si layer, with a first, second, and third photodiode formed as a stacked multi-junction structure; and,
forming a U-shaped well liner, fully isolating each photodiode set from adjacent photodiode sets in the array.
13. The method of claim 12 wherein forming the photodiode set includes forming each photodiode with a doped Si layer physically interfaced to the well liner.
14. The method of claim 13 wherein forming the well liner includes forming a well liner first wall physically interfaced to a doped Si layer of each photodiode.
15. The method of claim 14 wherein forming the photodiodes includes forming each photodiode with a p doped Si layer physically interfaced to the well liner; and,
wherein forming the well liner includes forming a p doped well liner electrically connected to a reference voltage.
16. The method of claim 15 wherein forming the well liner includes forming a well bottom physically interfaced to the first wall; and,
wherein forming the photodiodes includes forming the third, bottom-most, photodiode with a p doped layer that is part of the well bottom.
17. The method of claim 16 wherein forming the first photodiode includes forming the first photodiode with a first doped Si layer formed in a top surface region, and an underlying first p doped Si layer physically interfaced to the first wall;
wherein forming the second photodiode includes forming the second photodiode with a second doped Si layer underlying the first p doped Si layer, an underlying second p doped Si layer physically interfaced to the first wall, and an n doped first vertical structure physically interfacing the second doped Si layer to a top surface region; and,
wherein forming the third photodiode includes forming a third doped Si layer underlying the second p doped Si layer, an underlying third p doped Si layer physically interfaced to the first wall and forming a portion of the well bottom, and an n doped second vertical structure physically interfacing the third doped Si layer to a top surface region.
18. The method of claim 17 wherein forming the well liner includes forming a p doped second wall physically interfaced to the second vertical structure, the third doped Si layer, and the well bottom.
19. The method of claim 17 wherein forming the photodiode set includes forming first, second, and third n doped Si layers.
20. The method of claim 17 wherein forming the photodiode set includes forming a first n doped Si layer, and second and third p doped Si layers.
21. The method of claim 17 wherein forming the well liner includes:
prior to forming the photodiode set doped Si layers, p doping a horizontal layer of the Si substrate, forming the well bottom; and
p doping vertical sections, forming the well liner first and second walls.
22. The method of claim 21 wherein forming the well bottom includes:
doping with a boron concentration in a range of 5×10 16 to 1×10 19 per cubic centimeter (cm −3 );
forming a well bottom layer with a thickness in a range of about 0.5 to 2 microns; and,
forming the well bottom a depth in a range of about 2 to 6 microns below the top surface.
23. The method of claim 21 wherein forming the well liner first and second wall includes:
doping with a boron concentration in a range of 5×10 16 to 1×10 19 cm −3 ; and,
forming vertical structures extending a depth in a range of about 2 to 6 microns below the top surface.
24. The method of claim 12 wherein forming the photodiode set includes forming the photodiode set in the Si substrate.