IP Library Granted Patent US 7,616,053
Granted Patent B2
US 7,616,053 · App. 11/703,194 · Granted Nov 10, 2009

Power amplifier circuit and method for envelope modulation of high frequency signal

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,616,053
App. No.
11/703,194
Granted
Nov 10, 2009
Kind
B2
Abstract

A power amplifier circuit includes: a transformer receiving a first signal and generating a transformed signal from the first signal; and a transistor receiving a second signal having a direct current (DC) component, and generating an output signal. The second signal and the transformed signal are mixed, via a terminal connected with the transformed signal, wherein an envelope of the output signal is controlled by the first signal.

Claims (21)

1. A power amplifier circuit comprising:

a transformer which receives a first signal and generates a transformed signal from the first signal; and

a transistor which receives a second signal having a direct current (DC) component, and generates an output signal corresponding to a mixture of the second signal and the transformed signal, via a terminal connected with the transformed signal,

wherein an envelope of the output signal is controlled by the first signal.

2. The power amplifier circuit of claim 1 , wherein, two terminals of a first coil of the transformer respectively receive a first power source and the first signal, a first terminal of a second coil of the transformer is connected with a second power source, and a second terminal of the second coil generates the transformed signal.

3. The power amplifier circuit of claim 2 , wherein, a gate of the transistor receives the second signal, a first terminal among a drain and a source of the transistor is connected with the transformed signal, a second terminal among the drain and the source is connected with the first power source, and the first terminal generates the output signal.

4. The power amplifier circuit of claim 1 , further comprising:

an envelope shaper which generates the first signal by low pass filtering and amplifying an input analog signal.

5. The power amplifier circuit of claim 1 , further comprising:

a bias circuit which generates at least one DC component from a power source; and

a driver stage which generates the second signal from an input analog signal using at least one amplifier biased by the at least one DC component.

6. The power amplifier circuit of claim 5 , wherein the bias circuit comprises:

a second transformer which receives the first signal and generates a second transformed signal from the first signal,

wherein the second signal corresponds to a mixture of the second transformed signal and an analog signal having the DC component.

7. The power amplifier circuit of claim 1 , further comprising:

an impedance matching circuit connected with the output signal.

8. A signal amplification method comprising:

receiving a first signal to generate a transformed signal, by a transformer;

receiving a second signal having a DC component, by a transistor; and

generating an output signal corresponding to a mixture of the second signal and the transformed signal, via a terminal connected with the transformed signal, by the transistor,

wherein an envelope of the output signal is controlled by the first signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2007
From: KIM, SEUNG WOO; LEE, JEONG HOON; LEE, JAE SUP
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 018966/0017 →
Priority Claims (1)
KR 10-2006-0063909 · Jul 7, 2006 · national
Continuity (1)
Related Publication 20080008273A1 · Jan 10, 2008