IP Library › Granted Patent US 7,622,731
Granted Patent B2
US 7,622,731 · App. 11/709,631 · Granted Nov 24, 2009

Cross-point memory array

Assignee: Marvell World Trade Ltd
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Quick Facts
Patent No.
US 7,622,731
App. No.
11/709,631
Granted
Nov 24, 2009
Kind
B2
Abstract

A circuit comprises a bulk silicon integrated circuit (IC). A first metallization layer is arranged adjacent to said bulk silicon IC. Phase change memory (PCM) is arranged adjacent to said first metallization layer and comprises a plurality of PCM cells each including a phase-change material, a heater that selectively heats said phase-change material, and a diode in series with said phase-change material.

Claims (80)

1. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC;

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material, wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer; and

a conductive barrier material arranged between said first metallization layer and said diode.

2. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC; and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material,

wherein said diode includes crystallized islands chat are crystallized using a seeding metal layer and chat are crystallized from an amorphous silicon layer that is deposited over said first metallization layer, and

wherein said first metallization layer comprises copper.

3. The circuit of claim 1 wherein said barrier material comprises titanium nitride.

4. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC; and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that corn rises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material,

wherein said diode includes crystallized islands chat are crystallized using a seeding metal layer and chat are crystallized from an amorphous silicon layer that is deposited over said first metallization layer, and

wherein said seeding metal layer comprises nickel.

5. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC; and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material, wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer,

wherein said diode comprises an n-type layer,

wherein said seeding metal layer crystallizes said n-type layer, and

wherein said diode comprises a metal layer arranged adjacent to said n-type layer.

6. The circuit of claim 5 wherein said metal layer comprises titanium.

7. A system comprising:

a circuit comprising:

a bulk silicon integrated circuit (IC),

a first metallization layer that is arranged adjacent to said bulk silicon IC, and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including;

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material, wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer; and

a non-memory circuit that includes said first metallization layer, wherein said PCM is integrated with said non-memory circuit, and wherein said diode thermally communicates with said first metallization layer.

8. A system comprising:

a circuit comprising:

a bulk silicon integrated circuit (IC),

a first metallization layer that is arranged adjacent to said bulk silicon IC, and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material, wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer; and

a memory circuit that includes said first metallization layer, wherein said PCM is integrated with said memory circuit, and wherein said diode thermally communicates with said first metallization layer.

9. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC; and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that comprises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material,

wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer, and

wherein N bits of user data are stored in each of said plurality of PCM cells, where N is an integer greater than one.

10. A circuit comprising:

a bulk silicon integrated circuit (IC);

a first metallization layer that is arranged adjacent to said bulk silicon IC; and

phase change memory (PCM) that is arranged adjacent to said first metallization layer and that cormprises a plurality of PCM cells, each PCM cell including:

a phase-change material,

a heater that selectively heats said phase-change material, and

a diode in series with said phase-change material, wherein said diode includes crystallized islands that are crystallized using a seeding metal layer and that are crystallized from an amorphous silicon layer that is deposited over said first metallization layer,

wherein said heater includes a resistive material partially surrounding a dielectric material,

wherein said resistive material and said dielectric material form a first planar surface, and

wherein said phase-change material includes a second planar surface arranged adjacent to said first planar surface of said heater element.

11. The circuit of claim 10 ,

wherein said first metallization layer includes a first side and a second side,

wherein said bulk silicon IC comprises a transistor that is adjacent to said first side of said first metallization layer, and

wherein said diode is arranged adjacent to said second side of said first metallization layer.

12. The circuit of claim 5 wherein said metal layer of said diode is arranged between said n-type silicon layer and said heater.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
Continuity (3)
Continuation 1163796700 · Dec 13, 2006
Provisional Application 6078237900 · Mar 15, 2006
Related Publication 20070215910A1 · Sep 20, 2007