Semiconductor device with amorphous silicon MONOS memory cell structure and method for manufacturing thereof
View Patent ↗A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.
1. A method for making an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure, the method comprising:
providing a substrate;
forming a first insulation layer on the substrate;
forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an n-type a-Si layer, a barrier layer, and a conductive layer, the n-type a-Si layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of n-type a-Si;
forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface;
forming an i-type a-Si layer overlying the first surface and the second surface;
forming a p-type a-Si layer overlying the i-type a-Si layer;
forming an oxide-nitride-oxide (ONO) layer overlying the p-type a-Si layer;
forming a metal layer overlying the ONO layer; and
forming at least one control gate by patterning the metal layer.
2. The method of claim 1 wherein the method of forming one or more source or drain regions on the first insulation layer further comprises:
depositing the conductive layer on the first insulation layer;
depositing the barrier layer overlying the conductive layer;
depositing the n-type a-Si layer overlying the barrier layer; and
patterning the n-type a-Si layer, the barrier layer, and the conductive layer to form a confined region including the first surface.
3. The method of claim 2 wherein the conductive layer is metal silicide comprising TiSi 2 .
4. The method of claim 2 wherein the barrier layer is metal nitride comprising TiN.
5. The method of claim 1 wherein the first insulation layer comprises silicon dioxide.
6. The method of claim 1 wherein forming a second insulation layer on the first insulation layer further comprises:
depositing the second insulation layer to cover one or more source or drain regions on the first insulation layer; and
performing CMP and/or etch back process so as to form the second surface, the second surface being substantially co-planar with the first surface.
7. The method of claim 6 wherein the second insulation layer comprises silicon oxide deposited by high-density-plasma-assisted chemical vapor deposition.
8. The method of claim 6 wherein the second insulation layer comprises TEOS deposited silicon oxide.
9. The method of claim 1 wherein the i-type a-Si layer includes substantially intrinsic silicon material.
10. The method of claim 1 wherein the p-type a-Si layer overlying the i-type a-Si layer is capable of forming an amorphous silicon PIN diode junction at the first surface.
11. The method of claim 1 wherein the p-type a-Si layer overlying the i-type a-Si layer is capable of forming a p-channel connecting the n-type a-Si source region and a n-type a-Si drain region.
12. The method of claim 1 wherein forming the amorphous silicon layer further comprises depositing amorphous silicon layer by Si 2 H 6 with low pressure chemical vapor deposition (LP-CVD) method under 450 Degree Celsius or by SiH 4 with plasma CVD or by SiH 4 or Si 2 H 6 with atomic layer deposition (ALD) method.
13. The method of claim 1 wherein forming the ONO layer further comprises:
depositing a silicon oxide tunnel layer on the p-type a-Si layer;
depositing a silicon nitride layer overlying the silicon oxide tunnel layer; and
depositing a silicon oxide block layer overlying the silicon nitride layer.
14. The method of claim 12 wherein forming the ONO layer is performed by using an atomic-layer deposition (ALD) technique.
15. The method of claim 1 wherein the metal layer overlying the ONO layer comprises aluminum material.
16. The method of claim 1 wherein the metal layer overlying the ONO layer comprises titanium material.
17. The method of claim 1 wherein the control gate is positioned over at least one source and one drain region.
18. The method of claim 1 further comprising repeating the process steps to stack the memory cell structures three-dimensionally.