IP Library › Granted Patent US 7,626,472
Granted Patent B2
US 7,626,472 · App. 11/729,558 · Granted Dec 1, 2009

Package embedded three dimensional balun

Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,626,472
App. No.
11/729,558
Granted
Dec 1, 2009
Kind
B2
Abstract

Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.

Claims (22)

1. A substrate comprising:

a first metal layer;

a second metal layer; and

one or more capacitor layers,

wherein the first and second metal layers and the one or more capacitor layers form a balun and wherein the one or more capacitor layers are located between the first metal layer and the second metal layer.

2. The substrate of claim 1 , wherein the first metal layer comprises a spiral portion to form a first inductor and sections of a second inductor and the second metal layer comprises a spiral portion to form a second inductor and sections of the first inductor.

3. The substrate of claim 2 , wherein the first and second inductors form the transformer portion of the balun.

4. The substrate of claim 1 , wherein the capacitor layers are etched to form fully isolated capacitor islands.

5. The substrate of claim 1 , wherein the capacitor layers are extended over an entire length and width of the substrate.

6. The substrate of claim 1 , further comprising a plurality of dielectric layers coupled to one or more of the first metal layer, the second metal layer, or one or more of the capacitor layers.

7. The apparatus of claim 1 , further comprising a symmetric on-package transformer that comprises a first inductor and a second inductor, wherein the first metal layer comprises a spiral portion to form the first inductor and sections of the second inductor and the second metal layer comprises a spiral portion to form a second inductor and sections of the first inductor.

8. The substrate of claim 1 , further comprising a third metal layer that is electrically coupled to the first metal layer and a fourth metal layer that is electrically coupled to the second metal layer.

9. The substrate of claim 8 , further comprising one or more solder resist layers coupled to the top and bottom most metal layers.

10. A method comprising:

providing a first metal layer;

providing a second metal layer; and

providing a capacitor layer,

wherein the first and second metal layers and the capacitor layer form a balun and wherein the one or more capacitor layers are located between the first metal layer and the second metal layer.

11. The method of claim 10 , further comprising coupling portions of the first metal layer through one or more vias to form a first spiral portion and coupling portions of the second metal layer through one or more vias to form a second spiral portion.

12. The method of claim 10 , further comprising etching the capacitor layer.

13. The method of claim 10 , further comprising a plurality of dielectric layers coupled to one or more of the first metal layer, the second metal layer, or the capacitor layer.

14. The method of claim 10 , further comprising embedding the balun and one or more other baluns in a multilayer organic substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2008
From: DAVIES-VENN, EMILE; KAMGAING, TELESPHOR
To: INTEL CORPORATION
Reel/Frame 021642/0717 →
Continuity (1)
Related Publication 20080238568A1 · Oct 2, 2008