The present invention discloses an N-ary mask-programmable memory (N-MPM). N-MPM cells can have N cell-states, with N>2. N-MPM cells could be geometry-defined, junction-defined, or both. Based on an nF-opening process (n≧1), partial-contacts with feature size <1F can be implemented with an nF-opening mask with feature size ≧1F. N can be a non-integral power of 2. In this case, each memory cell represents fractional bits.
1. An N-ary mask-programmable memory, comprising:
a plurality of lower address-selection lines;
a plurality of upper address-selection lines above said lower address-selection lines;
a plurality of mask-programmable memory cells coupled to said lower and upper address-selection lines, each of said memory cells comprising a diode-like device and having one of at least N possible cell-states with N>2;
wherein, memory cells in a same cell-state have substantially the same geometry, and memory cells in at least three different cell-states have different geometries and have different ranges of read current at a read voltage.
2. The N-ary mask-programmable memory according to claim 1 , further comprising a memory cell coupled to a lower address-selection line and an upper address-selection line, said memory cell further comprising a contact-area smaller than the overlapping area between said lower and upper address-selection lines, wherein said contact-area is the smallest current conduction area in said memory cell.
3. The N-ary mask-programmable memory according to claim 2 , wherein an edge of said contact-area aligns with an edge of said upper address-selection line.
4. The N-ary mask-programmable memory according to claim 3 , further comprising:
a first memory cell coupled to a first upper address-selection line, said first memory cell having a first contact-area, an edge of said first contact-area aligning with a first edge of said first upper address-selection line;
a second memory cell coupled to a second upper address-selection line, said second memory cell having a second contact-area, an edge of said second contact-area aligning with a second edge of said second upper address-selection line;
wherein said first and second upper address-selection lines are adjacent and parallel, and said first and second edges are opposite.
5. The N-ary mask-programmable memory according to claim 2 , wherein the sizes of contact-areas from different cell-states are unevenly distributed.
6. The N-ary mask-programmable memory according to claim 1 , further comprising a plurality of vertically stacked memory levels, wherein said mask-programmable memory cells are located in at least one of said memory levels.
7. The N-ary mask-programmable memory according to claim 1 , wherein N is a non-integral power of 2, and said mask-programmable memory further comprises means for converting N-ary data to binary.
8. The N-ary mask-programmable memory according to claim 1 , wherein memory cells in at least two different cell-states have different junctions.
9. An N-ary mask-programmable memory, comprising:
a plurality of lower address-selection lines;
a plurality of upper address-selection lines above said lower address-selection lines;
a plurality of mask-programmable memory cells coupled to said lower and upper address-selection lines, each of said memory cells comprising a diode-like device and having one of at least N possible cell-states with N>2;
wherein, memory cells in a same cell-state have substantially the same junction, and memory cells in at least two different cell-states have different junctions and have different ranges of read current at a read voltage.
10. The N-ary mask-programmable memory according to claim 9 , wherein said diode-like device has a doping profile, and memory cells in at least two different cell-states have different doping profiles.
11. The N-ary mask-programmable memory according to claim 9 , further comprising means for limiting the read current through the memory cell under read.
12. The N-ary mask-programmable memory according to claim 9 , wherein at least two read voltages are applied in sequence to a selected memory cell during read.
13. The N-ary mask-programmable memory according to claim 9 , further comprising a plurality of vertically stacked memory levels, wherein said mask-programmable memory cells are located in at least one of said memory levels.
14. The N-ary mask-programmable memory according to claim 9 , wherein N is a non-integral power of 2, and said mask-programmable memory further comprises means for converting N-ary data to binary.
15. The N-ary mask-programmable memory according to claim 9 , wherein memory cells in at least two different cell-states have different geometries.
16. An N-ary mask-programmable memory, comprising:
a plurality of lower address-selection lines;
a plurality of upper address-selection lines above said lower address-selection lines;
a plurality of mask-programmable memory cells and dummy cells coupled to said lower and upper address-selection lines, each of said memory cells comprising a diode-like device and having one of at least N possible cell-states with N>2, wherein memory cells in different cell-states have different ranges of read current at a read voltage;
means for comparing a first input from a selected memory cell and a second input from a selected dummy cell.
17. The N-ary mask-programmable memory according to claim 16 , wherein said second input is coupled to first and second dummy cells, said first dummy cell having a first one of said N cell-states and said second dummy cell having a second one of said N cell-states.
18. The N-ary mask-programmable memory according to claim 16 , wherein memory cells in at least three different cell-states have different geometries.
19. The N-ary mask-programmable memory according to claim 16 , wherein memory cells in at least two different cell-states have different junctions.
20. The N-ary mask-programmable memory according to claim 16 , wherein N is a non-integral power of 2, and said mask-programmable memory further comprises means for converting N-ary data to binary.