Corresponding capacitor arrangement and method for making the same
The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
1. A capacitor arrangement comprising:
a first capacitor electrode having a multiplicity of interspaced first interconnects;
a capacitor dielectric formed at the surface of the first interconnects;
a second capacitor electrode having a multiplicity of interspaced second interconnects formed on the capacitor dielectric and between the first interconnects;
wherein the first and second capacitor electrodes are formed in a top layer of a first insulating layer, the top layer being formed on a bottom layer with an etching stop layer; and
wherein the bottom layer and the top layer of the first insulating layer have an identical material with an intervening additional etching stop layer.
2. A capacitor arrangement comprising:
a first capacitor electrode having a multiplicity of interspaced first interconnects;
a capacitor dielectric formed at the surface of the first interconnects;
a second capacitor electrode having a multiplicity of interspaced second interconnects formed on the capacitor dielectric and between the first interconnects;
wherein the first and second capacitor electrodes are formed in a top layer of a first insulating layer, the top layer being formed on a bottom layer with an etching stop layer; and
wherein the first capacitor electrode is formed in comb-shaped fashion with a peripheral interconnect surrounding the first interconnects, at least one partial section of the peripheral interconnect being at a distance from the first interconnects, the distance being greater than the width of a contact or a via region.
3. The capacitor arrangement as claimed in claim 1 , wherein the first interconnects are formed in a rectilinear, meandering, zigzag or cross-lattice-shaped fashion.
4. The capacitor arrangement as claimed in claim 1 , wherein the capacitor arrangement is a BEOL-MIMCap.
5. The capacitor arrangement as claimed in claim 1 , wherein the first and second capacitor electrodes are formed in a bottommost metalization level of an integrated semiconductor circuit arrangement.
6. The capacitor arrangement as claimed in claim 1 , wherein:
the first insulating layer has a porous or a non-porous low-k material, in particular FSG or OSG, and/or SiO 2 ;
the first and second capacitor electrodes have Cu, Al and/or Ag; and
the capacitor dielectric has a high-k material, in particular Al 2 O 3 , HfO 2 or SiC.