Multi layer low cost cavity substrate fabrication for pop packages
In a method and system for fabricating a semiconductor device ( 100 ) having a package-on-package structure, a base laminate substrate (BLS) ( 110 ) is formed to include a base center portion ( 112 ) and a peripheral portion ( 114 ) separated by a barrier element ( 120 ). The barrier element ( 120 ) forms a peripheral wall ( 118 ) to surround the base center portion ( 112 ). A frame shaped top laminate substrate (TLS) ( 130 ) is disposed over the peripheral portion ( 114 ) of the BLS ( 110 ). The TLS ( 130 ) has an open top center portion ( 132 ) matching the base center portion ( 112 ) surrounded by the peripheral wall ( 118 ) to form a cavity ( 140 ). A plurality of conductive bumps ( 150 ) each disposed between a top contact pad ( 134 ) of the TLS and a base contact pad ( 116 ) of the peripheral portion ( 114 ) of the BLS ( 110 ) are formed to provide electrical and mechanical coupling therebetween. The barrier element ( 120 ) forms a seal between the cavity ( 140 ) and the plurality of conductive bumps ( 150 ).
1. A semiconductor device comprising:
a base laminate substrate having a base center portion and a peripheral portion separated by a barrier element, the barrier element forming a peripheral wall to surround the base center portion;
a picture-frame shaped top laminate substrate disposed over the peripheral portion of the base laminate substrate, the top laminate substrate having an open top center portion matching the base center portion surrounded by the peripheral wall to form a cavity; and
a plurality of conductive bumps, each one of the plurality of conductive bumps disposed between a top contact pad of the top laminate substrate and a base contact pad of the peripheral portion of the base laminate substrate to provide electrical and mechanical coupling therebetween, the barrier element forming a seal between the cavity and the plurality of conductive bumps.
2. The device of claim 1 further comprising:
at least one die attached to the base center portion; and
a molding compound to encapsulate the at least one die and fill the cavity, wherein a region disposed between the top laminate substrate, the base laminate substrate and the seal is void of the molding compound.
3. The device of claim 2 , wherein the at least one die is selectable to be one of a flip chip die and a wirebond die.
4. The device of claim 2 , wherein the at least one die includes a first die mountable as a flip chip die and a second die stackable on the first die, the second die being mountable as a wirebond die.
5. The device of claim 2 , wherein the at least one die includes a first die mountable as a wirebond package and a second die stackable on the first die, the second die being mountable as another wirebond package.
6. The device of claim 2 , wherein the at least one die is one of a microprocessor, a digital signal processor, a radio frequency chip, a memory, a microcontroller, and a system-on-a-chip or a combination thereof.
7. The device of claim 1 , wherein a height of the barrier element is equal to a height of one of the plurality of conductive bumps added to a height for each one of the top and the base contact pads.
8. The device of claim 1 , wherein the barrier element is formed from one of a solder resist material and an adhesive material.
9. The device of claim 1 , wherein the top laminate substrate includes at least one metal layer.
10. The device of claim 1 , wherein the barrier element abuts a bottom surface of top laminate substrate to form the seal.
11. The device of claim 1 , wherein the plurality of conductive bumps are fabricated from a reflowable solder paste material.
12. The device of claim 11 , wherein the base laminate substrate is fabricated from one of an organic substrate, a ceramic substrate, a glass epoxy substrate, and a bismaleimide triazine (BT) substrate.
13. The device of claim 1 , wherein a bottom surface of the top laminate substrate excluding the top contact pads is coated with a layer of a solder resist material.