Semicondutor device and protection circuit
In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10 A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector thereof is connected to a low-potential power supply terminal VSS. In a second PNP type bipolar transistor 10 B, the emitter thereof is connected to the input/output terminal I/O, and the base and the collector thereof are connected to the high-potential power supply terminal VDD. In a third PNP type bipolar transistor 10 C, the emitter thereof is connected to the low-potential power supply terminal VSS, and the base and the collector thereof are connected to the high-potential power supply terminal VDD.
1. A semiconductor device comprising:
a well formed in a region where a protection circuit of an input/output terminal is disposed;
a plurality of emitter diffusion layers formed on the well and having a conductivity type opposite to the conductivity type of the well;
a plurality of first collector diffusion layers formed on the well and having a conductivity type opposite to the conductivity type of the well;
a plurality of second collector diffusion layers formed on the well and having a conductivity type opposite to the conductivity type of the well;
a base diffusion layer formed on the well and having the same conductivity type as the conductivity type of the well; and
an insulating layer isolating the emitter diffusion layers, the first collector diffusion layers, the second collector diffusion layers, and the base diffusion layer, respectively, wherein
a first bipolar transistor is composed of the emitter diffusion layers, the first collector diffusion layers, and the base diffusion layer,
a second bipolar transistor is composed of the emitter diffusion layers, the second collector diffusion layers, and the base diffusion layer,
a third bipolar transistor is composed of the first collector diffusion layers, the second collector diffusion layers, and the base diffusion layer,
the emitter diffusion layers are electrically connected to the input/output terminal,
first collector diffusion layers are electrically connected to a first power supply terminal, and
the second collector diffusion layers and the base diffusion layer are electrically connected to a second power supply terminal.
2. The semiconductor device according to claim 1 , wherein
the emitter diffusion layers and the first collector diffusion layers are alternatively arranged in a row direction and a column direction in a dotted manner; and
the second collector diffusion layers are arranged in a dotted manner, one in each row, at one end in a first row and at the other end in a second row, and adjacent to a predetermined emitter diffusion layers.
3. The semiconductor device according to claim 1 , wherein
the base diffusion layer is arranged in a striped manner at the peripheries of the emitter diffusion layers, the first collector diffusion layers, and the second collector layers.
4. The semiconductor device according to claim 1 , comprising:
a first wiring electrically connected to the emitter diffusion layer and electrically connected to the input/output terminal through a contact pug;
a second wiring electrically connected to the first collector diffusion layer and electrically connected to the first power supply terminal through a contact pug; and
a third wiring electrically connected to the second collector diffusion layer and the base diffusion layer and electrically connected to the second power supply terminal through a contact pug, wherein
the first wiring, the second wiring, and the third wiring are formed in a same wiring layer.
5. The semiconductor device according to claim 4 , comprising:
a fourth wiring electrically connected to the third wiring and electrically connected to the second power supply terminal, through a contact via; and
a fifth wiring electrically connected to the second wiring and electrically connected to the first power supply terminal, through a contact via, wherein
the fourth wiring and the fifth wiring are formed in a same wiring layer.
6. The semiconductor device according to claim 1 , wherein said first power supply terminal is a low potential power supply terminal and said second power supply terminal is a high potential power supply terminal.