Multi-level non-volatile memory cell with high-VT enhanced BTBT device
View Patent ↗The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.
1. A Non-Volatile Memory (NVM) cell capable of denoting at least two distinct logic levels, comprising:
a read-transistor having a floating gate;
at least a first Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor, the first BTBT device configured as an injection device for injecting a first charge onto the floating gate when the first BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels; and
a first electrode coupled to bias the first BTBT device with a first bias voltage that will put the BTBT device into accumulation during charge injection.
2. The cell of claim 1 , in which
the BTBT device has a gate dielectric and a well region, and
the first electrode is coupled to the well region for biasing the first BTBT device, the biasing resulting in a self extinguishing band-to-band-tunneling current within a semiconductor substrate of the BTBT device, the band-to-band-tunneling current inducing an injection current that flows through a gate dielectric into the floating gate to establish a first amount of electric charge on the floating gate.
3. The cell of claim 1 , in which
an injected amount of charge on the floating gate is determined by the first bias voltage.
4. The cell of claim 1 , further comprising:
a third transistor coupled in series with the first BTBT device, a first select line being coupled to the third transistor, the third transistor providing a current to the first BTBT device during a memory write operation; and
a fourth transistor coupled in series with the read-transistor, a second select line being coupled to the fourth transistor, the fourth transistor providing a current to the read-transistor during a memory read operation.
5. The cell of claim 1 , further comprising:
a fifth transistor having a fifth gate that is part of the floating gate, the fifth transistor used for Fowler-Nordheim tunneling to move charge onto the floating gate.
6. The cell of claim 1 , further comprising:
a bias-capacitor coupled to the floating gate, and
in which the bias-capacitor is used to further adjust a voltage level on the floating gate during a write operation.
7. The cell of claim 1 , further comprising:
a second BTBT device complementary to the first BTBT device, the second BTBT device sharing the floating gate with the first BTBT device and capable of injecting a second charge onto the floating gate that has a polarity opposite to that of the first charge.
8. The cell of claim 7 , in which
the first BTBT device is of a polarity opposite to a polarity of the second BTBT device.
9. The cell of claim 7 , in which
the second BTBT device is coupled in series with the first BTBT device.
10. The cell of claim 7 , in which
the second BTBT device is coupled in parallel with the first BTBT device.
11. The cell of claim 7 , in which
a second electrode is coupled to a well region of the second BTBT device, for biasing the second BTBT device with a third bias voltage that puts the second BTBT device in accumulation during the write operation.
12. The cell of claim 1 , in which
a section of the floating gate that is part of the first BTBT device is formed from a doped poly.
13. The cell of claim 12 , in which
the first BTBT device is a NMOS device that has no LDD implant, and
the gate is doped with N-type impurities.
14. The cell of claim 12 , in which
the first BTBT device is a PMOS device that has no LDD implant, and
the gate is doped with P-type impurities.
15. The cell of claim 1 , further comprising:
a select transistor, and
in which a gate dielectric of the first BTBT device is thicker than a gate dielectric of the select transistor.
16. The cell of claim 1 , in which
a doping level in at least part of the channel region of the first BTBT device is higher than a doping level in a channel region of the read-transistor.
17. The cell of claim 1 , in which
a doping level in a region under a spacer next to the gate of the first BTBT device is higher than a doping level of another device having a substantially similar gate oxide thickness.
18. The cell of claim 1 , in which
the BTBT device is connected in such a way that charge injection onto the floating gate is prevented by the device through other means than a BTBT induced injection.
19. The cell of claim 1 , in which
the cell is capable of denoting at least four distinct logic levels, and
the floating gate can achieve four distinct charge levels corresponding to the four distinct logic levels.
20. A method of operating a non-volatile memory (NVM) cell having a floating gate that can be charged with amounts of charge representing at least two respective logic levels, the cell having at least a first Band-To-Band-Tunneling device (BTBT device) configured to inject a predetermined amount of charge onto the floating gate, comprising:
applying a first bias voltage to the cell, the first bias voltage being as such that it keeps the first BTBT device in accumulation, and to charge the floating gate to a first charging level corresponding to one of the logic levels; and
continuing to apply the first bias voltage until a conductive channel region is formed in the BTBT device.
21. The method of claim 20 , in which
the charge buildup on the floating gate stops when a conductive channel region is formed under the gate of the BTBT device.
22. The method of claim 20 , further comprising:
removing the first bias voltage after a depletion region is formed in the conductive channel region.
23. The method of claim 20 , further comprising:
determining the first bias voltage for the write operation that is appropriate for the desired logic level.
24. The method of claim 20 , in which
the cell includes a program select line coupled to the first BTBT device, and further comprising: activating the program select line to permit a current to flow through the first BTBT device.
25. The method of claim 20 , in which
an injected amount of charge on the floating gate is substantially independent of a duration of an application of the first bias voltage.