IP Library Granted Patent US 7,656,024
Granted Patent B2
US 7,656,024 · App. 11/427,906 · Granted Feb 2, 2010

Chip module for complete power train

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 7,656,024
App. No.
11/427,906
Granted
Feb 2, 2010
Kind
B2
Abstract

A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.

Claims (27)

1. A chip module comprising:

a circuit substrate having lateral dimensions;

a semiconductor die comprising a power transistor mounted on the circuit substrate; and

a passive electronic component stacked on the semiconductor die, and being in electrical and thermal communication with the semiconductor die, the passive electronic component having lateral dimensions that substantially correspond to lateral dimensions of the circuit substrate, wherein the passive electronic component is configured to be exposed to air flow such that it dissipates heat generated by the semiconductor die.

2. The chip module of claim 1 wherein the passive electronic component is an inductor.

3. The chip module of claim 1 further comprising a plurality of solder structures electrically and mechanically coupling the semiconductor die to the circuit substrate.

4. The chip module of claim 1 wherein the power transistor is a power MOSFET.

5. The chip module of claim 1 wherein the semiconductor die is a first semiconductor die, and the power transistor is a first power transistor, and wherein the chip module comprises a second semiconductor die, wherein the second semiconductor die comprises a second power transistor, and wherein the first and second semiconductor dies are present in ball grid array (BGA) type semiconductor die packages.

6. The chip module of claim 5 wherein the chip module forms at least part of a synchronous buck converter circuit.

7. The chip module of claim 1 , wherein the passive electronic component is a first passive electronic component and wherein the chip module comprises a second passive electronic component, wherein the second passive electronic component is mounted on the circuit substrate.

8. The chip module of claim 1 further comprising a first set of solder structures disposed between the semiconductor die and a first surface of the circuit substrate, and a second set of solder structures at the second surface of the circuit substrate.

9. The chip module of claim 1 further comprising a resilient, thermally conductive material between the passive electronic component and the semiconductor die.

10. The chip module of claim 9 wherein the resilient, thermally conductive material has elastomeric properties.

11. The chip module of claim 9 wherein the resilient, thermally conductive material is a preformed polymeric layer.

12. An electrical assembly comprising:

a motherboard; and

the chip module of claim 1 mounted on the motherboard.

13. The chip module of claim 1 wherein the passive electronic component serves as a heat sink.

14. A chip module comprising:

a circuit substrate having lateral dimensions;

a semiconductor die mounted on the circuit substrate; and

an electronic component comprising a coil stacked on the semiconductor die, and being in electrical and thermal communication with the semiconductor die, the electronic component having lateral dimensions that substantially correspond to the lateral dimensions of the circuit substrate, wherein the electronic component is configured to be exposed to air flow such that it dissipates heat generated by the semiconductor die.

15. The chip module of claim 14 wherein the semiconductor die comprises a power MOSFET and the electronic component is an inductor.

16. The chip module of claim 14 further comprising a plurality of solder structures electrically and mechanically coupling the semiconductor die to the circuit substrate.

17. The chip module of claim 16 wherein the plurality of solder structures are coupled to a first side of the semiconductor die, and further wherein an elastomeric, resilient, and thermally conductive layer couples a second side of the semiconductor die to the electronic component.

18. The chip module of claim 14 wherein the chip module has a height and the electronic component has a height, further wherein the height of the chip module is only slightly more than the height of the electronic component.

19. The chip module of claim 14 wherein the chip module has dimensions of less than 1 cubic inch and can provide at least 350 Watts of power at 1.3 Volts.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2009
From: ELBANHAWY, ALAN; TJIA, BENNY
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 023374/0979 →
Continuity (1)
Related Publication 20080001279A1 · Jan 3, 2008