Method of fabricating semiconductor devices having a recessed active edge
A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided.
1. A method of fabricating a semiconductor device, comprising:
forming an isolation layer in a substrate to define an active region;
forming a recessed region on at least one edge of the active region adjacent to the isolation layer, the recessed region having a first top surface lower than a second top surface of a central portion of the active region;
forming a gate electrode crossing over the active region; and
forming a source region and a drain region in the active region on both sides of the gate electrode, respectively,
wherein a top surface of the active region has a first length between the source region and the drain region crossing the recessed region longer than a second length between the source region and the drain region crossing the central point,
wherein a first channel length of the at least one edge of the active region is longer than a second channel length of the central portion, and
wherein a gate extension is formed in the recessed region to contact the gate electrode.
2. The method according to claim 1 , wherein forming the recessed region comprises:
forming a mask pattern on the active region and the isolation layer; and
selectively removing the edge of the active region using the mask pattern as an etch mask,
wherein a bottom of the recessed region is sloped down toward the isolation layer.
3. The method according to claim 2 , wherein a portion of the isolation layer is removed with the edge of the active region.
4. The method according to claim 1 , wherein the recessed region is formed to a smaller size than the resolution limit in a photolithography process.
5. The method according to claim 1 , before forming the gate electrode, further comprising forming a gate dielectric layer to cover an inner wall of the recessed region and a surface of the active region.
6. The method according to claim 1 , wherein forming the gate electrode comprises:
forming a conductive material layer on the substrate having the recessed region; and
patterning the conductive material layer,
wherein the gate extension is left in the recessed region.
7. The method according to claim 1 , wherein the gate electrode is formed to completely cover the recessed region.
8. The method according to claim 1 , wherein the gate electrode is formed to cover a portion of the recessed region.
9. The method according to claim 8 , wherein the gate extension extends on at least one side of the gate electrode, and wherein a top surface of the gate extension is disposed lower than or at substantially the same level as top surfaces of source and drain regions.
10. The method according to claim 1 , wherein the source and drain regions are disposed higher than the bottom of the recessed region.
11. The method according to claim 1 , wherein forming a recessed region on at least one edge of the active region includes forming a first recessed region on a first edge of the active region and forming a second recessed region on a second edge of the active region opposite the first edge.
12. The method of claim 11 , wherein each of the first and second recessed regions include a plurality of recessed portions.