IP Library › Granted Patent US 7,667,535
Granted Patent B2
US 7,667,535 · App. 12/073,610 · Granted Feb 23, 2010

Amplifier circuit with input terminals thereof connected to sampling capacitors

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,667,535
App. No.
12/073,610
Granted
Feb 23, 2010
Kind
B2
Abstract

Sampling capacitors are connected respectively to a pair of differential input terminals of an operational amplifier. The sampling capacitors sample input signals. Source terminals and drain terminals of dummy switches are connected respectively to paths connecting the operational amplifier and the sampling capacitors, so that a common-mode voltage of differential input voltages to the operational amplifier is adjusted by gate-channel capacitances.

Claims (24)

1. An amplifier circuit, comprising:

an operational amplifier including a pair of differential input terminals;

sampling capacitors, connected to the differential input terminals, respectively, which sample input signals;

a regulating capacitor, connected in parallel with one end of each of said sampling capacitors, which adjusts a common-mode voltage of differential input voltages to said operational amplifier; and

a first switch which short-circuits an output terminal and an input terminal of said operational amplifier,

wherein the regulating capacitor includes

a gate-channel capacitance of a second switch of which a source terminal and a drain terminal are connected to a path connecting said operational amplifier and said sampling capacitor,

the second switch is turned on during an amplifying period of said amplifier circuit and is turned off during a sampling period of said amplifier circuit, and

the first switch is turned off during an amplifying period of said amplifier circuit and is turned on during a sampling period of said amplifier circuit.

2. An amplifier circuit comprising:

an operational amplifier including a pair of differential input terminals;

sampling capacitors, connected to the differential input terminals, respectively, which sample input signals;

a regulating capacitor, connected in parallel with one end of each of said sampling capacitors, which adjusts a common-mode voltage of differential input voltages to said operational amplifier; and

a first switch which short-circuits an output terminal and an input terminal of said operational amplifier, wherein

the regulating capacitor includes a gate-channel capacitance of a second switch of which a source terminal and a drain terminal are connected to a path connecting said operational amplifier and said sampling capacitor,

the second switch is turned on during an amplifying period of said amplifier circuit so as to generate the gate-channel capacitance, and is turned off during a sampling period thereof so as to eliminate the gate-channel capacitance, and

wherein the second switch offsets a charge released to the path by turning off said first switch and using the gate-channel capacitance so as to adjusts potential of the path.

3. An amplifier circuit comprising:

an operational amplifier including a pair of differential input, terminals;

sampling capacitors, connected to the differential input terminals, respectively, which sample input signals; and

a regulating capacitor, connected in parallel with one end of each of said sampling capacitors, which adjusts a common-mode voltage of differential input voltages to said operational amplifier, wherein

one end of said regulating capacitor is connected to a path connecting said operational amplifier and said sampling capacitor, and a voltage which differs between during an amplifying period and during a sampling period of said amplifying circuit is inputted to the other end of said regulating capacitor,

a reference voltage is inputted to said sampling capacitor during the amplifying period, and

wherein the input signal is inputted to the other end of said regulating capacitor during the amplifying period, and the reference voltage is inputted thereto during the sampling period.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2008
From: KOBAYASHI, SHIGETO; WADA, ATSUSHI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 020676/0654 →
Priority Claims (1)
JP 2007-058296 · Mar 8, 2007 · national
Continuity (1)
Related Publication 20080218266A1 · Sep 11, 2008