IP Library › Granted Patent US 7,670,890

Granted Patent B2

US 7,670,890 · App. 11/493,229 · Granted Mar 2, 2010

Silicide block isolated junction field effect transistor source, drain and gate

Assignees: Texas Instruments Deutschland GmbH; Texas Instruments Incorporated

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Quick Facts

Patent No.: US 7,670,890
App. No.: 11/493,229
Granted: Mar 2, 2010
Kind: B2

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Abstract

An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.

Claims (192)

1. A method of forming a p type junction field effect transistor (PJFET) and an n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

forming a first n type buried layer (NBL1) in the substrate;

forming a first p type buried layer (PBL1) in the substrate, but laterally spaced from the NBL1;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming a second p type buried layer (PBL2) over the PBL1 in the NEPI1;

forming one or more DEEPNX regions over the NBL1 in the NEPI1;

forming a second n type epitaxial layer (NEPI2) over the NEPI1;

forming a p type surface shield near an upper surface of the NEPI2, where the p type surface shield resides over at least some of the PBL2;

forming an n type channel of the NJFET in the NEPI2, where the n type channel resides over at least some of the PBL2;

forming a p type bottom gate (BG) near a lower surface of the NEPI2, where the p type BG resides over at least some of the PBL2;

forming an n type surface shield near an upper surface of the NEPI2, where the n type surface shield resides over at least some of the NBL1;

forming a p type channel of the PJFET in the NEPI2, where the p type channel resides over at least some of the NBL1;

forming one or more isolation areas that isolate the PJFET from the NJFET at least by being formed between the NBL1 and the PBL1;

forming one or more n type back gate contact regions in the NEPI2 down to the one or more DEEPNX regions;

forming one or more p type back gate contact regions in the NEPI2 down to the PBL2;

forming a layer of silicide block material (SBLK) over the NEPI2;

patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed;

forming an n type gate region in the p type channel of the PJFET, and n type source and drain regions in the n type channel of the NJFET;

forming p type source and drain regions in the p type channel of the PJFET, and a p type gate region in the n type channel of the NJFET;

siliciding the gate, source and drain regions in the p type channel of the PJFET and in the n type channel of the NJFET;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2;

forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the p type channel of the PJFET and in the n type channel of the NJFET; and

forming a field plate over at least one of the conductive contacts extending down to one of the gate, source and drain regions of at least one of the PJFET and the NJFET, where the field plate also extends over at least some of at least one other of the gate, source and drain regions of the at least one of the PJFET and the NJFET.

2. The method of claim 1 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions of the at least one of the PJFET and the NJFET, where the field plate also extends over at least some of the gate region of the at least one of the PJFET and the NJFET.

3. A method of forming a p type junction field effect transistor (PJFET) in a semiconductor substrate, comprising:

forming a first n type buried layer (NBL1) in the substrate;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming one or more DEEPNX regions over the NBL1 in the NEPI1;

forming a second n type epitaxial layer (NEPI2) over the NEPI1;

forming an n type surface shield near an upper surface of the NEPI2, where the n type surface shield resides over at least some of the NBL1;

forming a p type channel in the NEPI2, where the p type channel resides over at least some of the NBL1;

forming one or more n type back gate contact regions in the NEPI2 down to the one or more DEEPNX regions;

forming a layer of silicide block material (SBLK) over the NEPI2;

patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed;

forming an n type gate region in the p type channel;

forming p type source and drain regions in the p type channel;

siliciding the gate, source and drain regions in the p type channel;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2;

forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the p type channel; and

forming a field plate over at least one of the conductive contacts extending down to one of the gate, source and drain regions, where the field plate also extends over at least some of at least one other of the gate, source and drain regions.

4. The method of claim 3 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions, where the field plate also extends over at least some of the gate region.

5. A method of forming an n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

forming a first p type buried layer (PBL1) in the substrate;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming a second p type buried layer (PBL2) over the PBL1 in the NEPI1;

forming a second n type epitaxial layer (NEPI2) over the NEPI1;

forming a p type surface shield near an upper surface of the NEPI2, where the p type surface shield resides over at least some of the PBL2;

forming an n type channel in the NEPI2, where the n type channel resides over at least some of the PBL2;

forming a p type bottom gate (BG) near a lower surface of the NEPI2, where the p type BG resides over at least some of the PBL2;

forming one or more p type back gate contact regions in the NEPI2 down to the PBL2;

forming a layer of silicide block material (SBLK) over the NEPI2;

patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed;

forming n type source and drain regions in the n type channel;

forming a p type gate region in the n type channel;

siliciding the gate, source and drain regions in the n type channel;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2;

forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the n type channel; and

6. The method of claim 5 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions, where the field plate also extends over at least some of the gate region.

7. A p type junction field effect transistor (PJFET) in a semiconductor substrate, comprising:

a first n type buried layer (NBL1) in the substrate;

a first n type epitaxial layer (NEPI1) over the substrate;

one or more DEEPNX regions over the NBL1 in the NEPI1;

a second n type epitaxial layer (NEPI2) over the NEPI1;

an n type surface shield near an upper surface of the NEPI2, where the n type surface shield resides over at least some of the NBL1;

a p type channel in the NEPI2, where the p type channel resides over at least some of the NBL1;

one or more n type back gate contact regions in the NEPI2 extending down to the one or more DEEPNX regions;

a silicided n type gate region in the p type channel;

silicided p type source and drain regions in the p type channel;

a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2;

conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions; and

a field plate over at least one of the conductive contacts extending down to one of the gate, source and drain regions, where the field plate also extends over at least some of at least one other of the gate, source and drain regions.

8. The PJFET of claim 7 , wherein the field plate is a field plate formed over at least one of the conductive contacts extending down to the source and drain regions and also extends over at least some of the gate region.

9. An n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

a first p type buried layer (PBL1) in the substrate;

a first n type epitaxial layer (NEPI1) over the substrate;

a second p type buried layer (PBL2) over the PBL1 in the NEPI1;

a second n type epitaxial layer (NEPI2) over the NEPI1;

a p type surface shield near an upper surface of the NEPI2, where the p type surface shield resides over at least some of the PBL2;

an n type channel in the NEPI2, where the n type channel resides over at least some of the PBL2;

a p type bottom gate (BG) near a lower surface of the NEPI2, where the p type BG resides over at least some of the PBL2;

one or more p type back gate contact regions in the NEPI2 extending down to the PBL2;

silicided n type source and drain regions in the n type channel;

a silicided p type gate region in the n type channel;

a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2;

conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions; and

10. The NJFET of claim 9 , wherein the field plate is a field plate formed over at least one of the conductive contacts extending down to the source and drain regions and also extends over at least some of the gate region.

11. A method of forming a junction field effect transistor (JFET) on a semiconductor substrate, comprising:

forming a layer of silicide block material over at least some of the substrate including over areas where source, drain and gate regions are to be formed in the substrate;

patterning the layer of silicide block material to expose areas of the substrate where the source, drain and gate regions are to be formed;

performing one or more doping operations to form a surface shield below a surface of the substrate including in areas where the source, drain and gate regions are formed in the substrate, and

performing one or more doping operations to form the source, drain and gate regions in the exposed areas of the substrate, where the source, drain and gate regions are self aligned with the patterned silicide block;

wherein the surface shield can be formed before or after the source, drain and gate regions are formed; and

wherein at least one of:

the source, gate and drain regions extend deeper into the substrate than the surface shield, and

the surface shield has dopant concentration that is less than the concentration of dopants in the source and drain regions.

12. The method of claim 11 , wherein forming the layer of silicide block material comprises:

forming a layer of oxide based material over at least some of the substrate including over areas where the source, drain and gate regions are to be formed in the substrate, and

forming a layer of nitride based material over the layer of oxide based material.

13. The method of claim 11 , further comprising forming a field plate over an electrically conductive gate contact, where the field plate also extends over at least some of at least one of the source region and the drain region.

14. The method of claim 11 , further comprising forming a field plate over an electrically conductive drain contact, where the field plate also extends over at least some of the gate region.

15. A method of forming a p type junction field effect transistor (PJFET) and an n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

forming a first n type buried layer (NBL1) in the substrate;

forming a first p type buried layer (PBL1) in the substrate, but laterally spaced from the NBL1;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming one or more DEEPNX regions over the NBL1 in the NEPI1;

forming a p type surface shield near an upper surface of the NEPI1, where the p type surface shield resides over at least some of the PBL1;

forming an n type channel of the NJFET in the NEPI1, where the n type channel resides over at least some of the PBL1;

forming a p type bottom gate (BG) near a lower surface of the NEPI1, where the p type BG resides over at least some of the PBL1;

forming an n type surface shield near an upper surface of the NEPI1, where the n type surface shield resides over at least some of the NBL1;

forming a p type channel of the PJFET in the NEPI1, where the p type channel resides over at least some of the NBL1;

forming one or more isolation areas that isolate the PJFET from the NJFET at least by being formed between the NBL1 and the PBL1;

forming one or more n type back gate contact regions in the NEPI1 down to the one or more DEEPNX regions;

forming one or more p type back gate contact regions in the NEPI1 down to the PBL1;

forming a layer of silicide block material (SBLK) over the NEPI1;

patterning the SBLK to expose areas of the NEPI1 where gate, source and drain regions are to be formed;

forming an n type gate region in the p type channel of the PJFET, and n type source and drain regions in the n type channel of the NJFET;

forming p type source and drain regions in the p type channel of the PJFET, and a p type gate region in the n type channel of the NJFET;

siliciding the gate, source and drain regions in the p type channel of the PJFET and in the n type channel of the NJFET;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI1;

16. A method of forming a p type junction field effect transistor (PJFET) in a semiconductor substrate, comprising:

forming a first n type buried layer (NBL1) in the substrate;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming one or more DEEPNX regions over the NBL1 in the NEPI1;

forming an n type surface shield near an upper surface of the NEPI1, where the n type surface shield resides over at least some of the NBL1;

forming a p type channel in the NEPI1, where the p type channel resides over at least some of the NBL1;

forming one or more n type back gate contact regions in the NEPI1 down to the one or more DEEPNX regions;

forming a layer of silicide block material (SBLK) over the NEPI1;

patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed;

forming an n type gate region in the p type channel;

forming p type source and drain regions in the p type channel;

siliciding the gate, source and drain regions in the p type channel;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI1;

forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the p type channel; and

17. A method of forming an n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

forming a first p type buried layer (PBL1) in the substrate;

forming a first n type epitaxial layer (NEPI1) over the substrate;

forming a p type surface shield near an upper surface of the NEPI1, where the p type surface shield resides over at least some of the PBL1;

forming an n type channel in the NEPI1, where the n type channel resides over at least some of the PBL1;

forming a p type bottom gate (BG) near a lower surface of the NEPI1, where the p type BG resides over at least some of the PBL1;

forming one or more p type back gate contact regions in the NEPI1 down to the PBL1;

forming a layer of silicide block material (SBLK) over the NEPI1;

patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed;

forming n type source and drain regions in the n type channel;

forming a p type gate region in the n type channel;

siliciding the gate, source and drain regions in the n type channel;

forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI1;

forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the n type channel; and

18. A p type junction field effect transistor (PJFET) in a semiconductor substrate, comprising:

a first n type buried layer (NBL1) in the substrate;

a first n type epitaxial layer (NEPI1) over the substrate;

one or more DEEPNX regions over the NBL1 in the NEPI1;

an n type surface shield near an upper surface of the NEPI1, where the n type surface shield resides over at least some of the NBL1;

a p type channel in the NEPI1, where the p type channel resides over at least some of the NBL1;

one or more n type back gate contact regions in the NEPI1 extending down to the one or more DEEPNX regions;

a silicided n type gate region in the p type channel;

silicided p type source and drain regions in the p type channel;

a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI1;

conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions; and

19. An n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising:

a first p type buried layer (PBL1) in the substrate;

a first n type epitaxial layer (NEPI1) over the substrate;

a p type surface shield near an upper surface of the NEPI1, where the p type surface shield resides over at least some of the PBL1;

an n type channel in the NEPI1, where the n type channel resides over at least some of the PBL1;

a p type bottom gate (BG) near a lower surface of the NEPI1, where the p type BG resides over at least some of the PBL1;

one or more p type back gate contact regions in the NEPI1 extending down to the PBL1;

silicided n type source and drain regions in the n type channel;

a silicided p type gate region in the n type channel;

a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI1;

conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions; and

a field plate over at least one of the conductive contacts extending down to one of the gate, source and regions, where the field plate also extends over at least some of at least one other of the gate, source and drain regions.

20. The method of claim 2 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions of each of the PJFET and the NJFET, where the field plate also extends over at least some of the gate region of the same PJFET and NJFET.

21. The method of claim 1 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region of each of the PJFET and the NJFET, where the field plate also extends over at least some of at least one of the source and drain regions of the same PJFET and NJFET.

22. The method of claim 21 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region of each of the PJFET and the NJFET, where the field plate also extends over at least some of both of the source and drain regions of the same PJFET and NJFET.

23. The method of claim 3 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region, where the field plate also extends over at least some of at least one of the source and drain regions.

24. The method of claim 23 , wherein the field plate formed over the conductive contact extending down to the gate region also extends over at least some of both of the source and drain regions.

25. The method of claim 5 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region, where the field plate also extends over at least some of at least one of the source and drain regions.

26. The method of claim 25 , wherein the field plate formed over the conductive contact extending down to the gate region also extends over at least some of both of the source and drain regions.

27. The PJFET of claim 7 , wherein the field plate is a field plate formed over the conductive contact extending down to the gate region and also extends over at least some of at least one of the source and drain regions.

28. The PJFET of claim 27 , wherein the field plate formed over the conductive contact extending down to the gate region also extends over at least some of both of the source and drain regions.

29. The NJFET of claim 9 , wherein the field plate is a field plate formed over the conductive contact extending down to the gate region and also extends over at least some of at least one of the source and drain regions.

30. The PJFET of claim 29 , wherein the field plate formed over the conductive contact extending down to the gate region also extends over at least some of both of the source and drain regions.

31. The method of claim 15 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions of at least one of the PJFET and the NJFET, where the field plate also extends over at least some of the gate region of the at least one of the PJFET and the NJFET.

32. The method of claim 31 , wherein forming the field plate comprises forming a field plate over at least one of the conductive contacts extending down to the source and drain regions of each of the PJFET and the NJFET, where the field plate also extends over at least some of the gate region of each of the same PJFET and NJFET.

33. The method of claim 15 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region of each of the PJFET and the NJFET, where the field plate also extends over at least some of at least one of the source and drain regions of each of the same PJFET and NJFET.

34. The method of claim 33 , wherein forming the field plate comprises forming a field plate over the conductive contact extending down to the gate region of each of the PJFET and the NJFET, where the field plate also extends over at least some of both of the source and drain regions of each of the same PJFET and NJFET.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2006

From: EL-KAREH, BADIH; BALSTER, SCOTT GERARD; TROGOLO, JOE R.; YASUDA, HIROSHI

To: TEXAS INSTRUMENTS INCORPORATED

Reel/Frame 018136/0569 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2006

From: STEINMANN, PHILLIP

To: TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Reel/Frame 018157/0335 →

Continuity (1)

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