Semiconductor device, method of manufacturing same, and apparatus for designing same
A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.
1. A method of manufacturing a semiconductor device, comprising:
forming a groove part, in which an interconnect to be connected to a semiconductor element is to be formed, and an insulating structure standing up from a bottom of the groove part; and
forming the interconnect by filling the groove part with a conductive material so as to surround the insulating structure with the conductive material.
2. The method as claimed in claim 1 , wherein said forming the interconnect includes filling the groove part by plating.
3. The method as claimed in claim 1 , wherein the structure is formed so as to divide a predetermined region of the interconnect into a plurality of portions.
4. The method as claimed in claim 1 , wherein the interconnect is a clock signal distribution line for distributing a clock signal.