Integrated circuit package substrate having configurable bond pads
Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.
1. A flip chip integrated circuit package, comprising:
a substrate having opposing first and second surfaces;
a solder mask layer that covers at least a portion of the first surface of the substrate, the first surface of the substrate having a first electrically conductive feature, a second electrically conductive feature, and a mounting region for a flip chip oriented integrated circuit die on the first surface of the substrate, the integrated circuit die having a plurality of solder bumps;
an opening in the solder mask layer overlapping the first electrically conductive feature and the second electrically conductive feature; and
an electrically conductive material;
wherein the first electrically conductive feature is a portion of a first electrical signal net of the substrate, and the second electrically conductive feature is a portion of a second electrical signal net of the substrate;
wherein the first electrically conductive feature is proximate to the second electrically conductive feature, and the first and second electrically conductive features are configured to be selectively electrically coupled together by application of the electrically conductive material; and
wherein the electrically conductive material is on the first surface at the opening and electrically couples the first electrically conductive feature and the second electrically conductive feature, wherein a solder bump of the plurality of solder bumps is the electrically conductive material.
2. The package of claim 1 , wherein the electrically conductive material is a conductive epoxy, a jumper, a solder paste, or a solder ball.
3. The package of claim 1 , wherein the second electrically conductive feature is formed in a ring that substantially surrounds the first electrically conductive feature.
4. The package of claim 3 , wherein the first electrically conductive feature has a substantially round shape and the second electrically conductive feature has a substantially round ring shape.
5. The package of claim 3 , wherein the first and second electrically conductive features each have a half-circle shape.
6. A substrate for a flip chip integrated circuit package, comprising:
a substrate body having opposing first and second surfaces;
a solder mask layer that covers at least a portion of the first surface of the substrate body;
a first electrically conductive feature on the first surface of the substrate body;
a second electrically conductive feature on the first surface of the substrate body that is proximate to the first electrically conductive feature;
an electrically conductive material;
an opening in the solder mask layer overlapping the first electrically conductive feature and the second electrically conductive feature; and
a mounting region for a flip chip oriented integrated circuit die on the first surface of the substrate body, the integrated circuit die having a plurality of solder bumps, wherein a solder bump of the plurality of solder bumps is the electrically conductive material;
wherein the first electrically conductive feature is a portion of a first electrical signal net of the substrate, and the second electrically conductive feature is a portion of a second electrical signal net of the substrate;
wherein the first and second electrically conductive features are configured to be selectively electrically coupled together by application of the electrically conductive material; and
wherein the electrically conductive material is on the first surface at the opening and electrically couples the first electrically conductive feature and the second electrically conductive feature.
7. The substrate of claim 6 , wherein the electrically conductive material is a conductive epoxy, a jumper, solder paste, or a solder ball.
8. The substrate of claim 6 , wherein the second electrically conductive feature is formed in a ring that substantially surrounds the first electrically conductive feature.
9. The substrate of claim 8 , wherein the first electrically conductive feature has a substantially round shape and the second electrically conductive feature has a substantially round ring shape.
10. The substrate of claim 6 , wherein the first and second electrically conductive features each have a half-circle shape.