Level-shifting circuit with bipolar junction transistor
A level-shifting circuit includes an input node, a first output transistor, a second output transistor, a pull-up transistor, and an output node. The input node receives an input signal. The first output transistor turns on when the input signal is at a first voltage level and couples an output node to a positive supply voltage when turned on. The second output transistor, a bipolar junction transistor (BJT), couples the output node to a negative supply voltage when turned on. The pull-up transistor turns on when the input signal is at a second voltage level and generates a voltage at a base terminal of the second output transistor that turns the second output transistor on. Additionally, the level-shifting circuit generates, at the output node, an output signal with a voltage swing that includes a positive voltage range and a negative voltage range.
1. A level-shifting circuit, comprising:
an input node operable to receive an input signal within an input voltage range;
a first output transistor operable to turn on when the input signal is at a first voltage level within the input voltage range and to couple an output node to a positive supply voltage when turned on;
a second output transistor operable to couple the output node to a negative supply voltage when turned on, wherein the second output transistor comprises a bipolar junction transistor; and
a pull-up transistor operable to:
turn on when the input signal is at a second voltage level; and
generate a voltage at a base terminal of the second output transistor that is sufficient to turn the second output transistor on; and
wherein the level-shifting circuit is operable to generate, at the output node, an output signal having a voltage level within an output voltage range and wherein a voltage swing associated with the output voltage range includes a positive voltage range and a negative voltage range.
2. The level-shifting circuit of claim 1 , wherein the first output transistor comprises a junction field effect transistor (JFET).
3. The level-shifting circuit of claim 2 , wherein the JFET is operable to turn on in response to a voltage differential of 0.5 volts being applied between a gate terminal of the JFET and a source terminal of the JFET.
4. The level-shifting circuit of claim 1 , wherein the pull-up transistor comprises a JFET.
5. The level-shifting circuit of claim 1 , further comprising a high-impedance element coupled to the base terminal of the second output transistor, and wherein a drain terminal of the pull-up transistor is coupled to the high-impedance element, and wherein current flows through the high-impedance element from the drain terminal of the pull-up transistor to the base terminal of the second output transistor when the pull-up transistor is turned on.
6. The level-shifting circuit of claim 1 , wherein the output voltage range is greater than the input voltage range.
7. The level-shifting circuit of claim 1 , wherein a maximum voltage of the output voltage range is greater than a maximum voltage of the input voltage range.
8. The level-shifting circuit of claim 1 , wherein the input voltage range comprises a voltage range between 0 volts and 0.5 volts and the output voltage range comprises a voltage range between −0.5 volts and 0.5 volt.
9. A method for processing signals, comprising:
receiving an input signal having a voltage level within an input voltage range at an input node;
coupling an output node to a first supply voltage though a first output transistor when the input signal is at a first voltage level within the input voltage range;
increasing a voltage level at a base terminal of a second output transistor to a level that is sufficient to turn the second output transistor on and wherein the second output transistor comprises a bipolar junction transistor (BJT);
coupling the output node to a second supply voltage through the second output transistor when the second output transistor is turned on;
generating, at the output node, an output signal having a voltage level within an output voltage range, wherein a voltage swing associated with the output voltage range includes a positive voltage range and a negative voltage range.
10. The method of claim 9 , wherein the first output transistor comprises a junction field effect transistor (JFET).
11. The method of claim 10 , wherein the JFET is operable to turn on in response to a voltage differential of 0.5 volts being applied between a gate terminal of the JFET and a source terminal of the JFET.
12. The method of claim 9 , wherein increasing a voltage level at the base terminal of the second output transistor comprises turning on a pull-up transistor when the input signal has a voltage equal to a second voltage level within the input voltage range, wherein the pull-up transistor, when turned on, is operable to increase the voltage level at the base terminal of the second output transistor.
13. The method of claim 12 , wherein the pull-up transistor comprises a JFET.
14. The method of claim 9 , wherein the output voltage range is greater than the input voltage range.
15. The method of claim 9 , wherein a maximum voltage of the output voltage range is greater than a maximum voltage of the input voltage range.
16. The method of claim 9 , wherein the input voltage range comprises a voltage range between 0 volts and 0.5 volts and the output voltage range comprises a voltage range between −0.5 volts and 0.5 volt.
17. A system for processing signals, comprising:
means for receiving an input signal having a voltage level within an input voltage range at an input node;
first switching means for coupling an output node to a first supply voltage when the input signal is at a first voltage level within the input voltage range;
means for increasing a voltage level at a base terminal of a bipolar junction transistor (BJT) associated with a second switching means to a level that is sufficient to turn on the BJT;
the second switching means for coupling the output node to a second supply voltage when the BJT is turned on;
means for generating, at the output node, an output signal having a voltage level within an output voltage range, wherein a voltage swing associated with the output voltage range includes a positive voltage range and a negative voltage range.
18. The system of claim 17 , wherein the first switching means comprises a junction field effect transistor (JFET).
19. The system of claim 18 , wherein the first switching means is operable to turn on in response to a voltage differential of 0.5 volts being applied between a gate terminal associated with the JFET and a source terminal associated with the JFET.
20. The system of claim 17 , wherein the means for increasing the voltage level at the base terminal of the BJT the comprises a JFET.
21. The system of claim 17 , wherein the output voltage range is greater than the input voltage range.
22. The system of claim 17 , wherein a maximum voltage of the output voltage range is greater than a maximum voltage of the input voltage range.
23. The system of claim 17 , wherein the input voltage range comprises a voltage range between 0 volts and 0.5 volts and the output voltage range comprises a voltage range between −0.5 volts and 0.5 volt.