IP Library Granted Patent US 7,689,133
Granted Patent B2
US 7,689,133 · App. 11/510,729 · Granted Mar 30, 2010

Optical signal reception device and method of controlling optical signal reception

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,689,133
App. No.
11/510,729
Granted
Mar 30, 2010
Kind
B2
Abstract

An optical signal reception device is disclosed that receives and demodulates an optical signal modulated by DQPSK and performs logical inversion and other controls to transit to the object reception state. The signal reception device includes a front end including a delay interferometer and an opto-electric conversion element that receive the DQPSK optical signal and convert it into an in-phase signal and a quadrature-phase signal, a clock regenerator that regenerates a clock signal based on the in-phase signal and the quadrature-phase signal, a multiplexer that multiplexes the in-phase signal and the quadrature-phase signal, a reception frame processing unit that detects frame synchronization based on the signal multiplexed by the multiplexer and de-maps the received frames, and a controller that, based on out-of-frame-synchronization information (LOF/OOF) from the reception frame processing unit, performs logical inversion control in the clock regenerator, multiplexing timing control in the multiplexer, and controls the delay interferometer in the front end so as to transit to the object reception state.

Claims (33)

1. A signal reception device for receiving and demodulating an optical signal modulated by a Differential Quadrature Phase Shift Keying (DQPSK) modulation scheme, said signal reception device comprising:

a front end including two delay interferometers and opto-electric conversion elements that receives the DQPSK optical signal and converts the DQPSK optical signal into an in-phase signal and a quadrature-phase signal;

a clock and data recovery that regenerates a clock and a data signal based on the in-phase signal and the quadrature-phase signal;

a multiplexer that multiplexes the in-phase signal and the quadrature-phase signal output from the clock and data recovery;

a reception frame processing unit that detects frame synchronization based on the signal multiplexed by the multiplexer; and

a controller that, based on a detection result from the reception frame processing unit indicating an out-of-frame-synchronization state, controls logical inversion operations in the clock and data recovery and controls a multiplexing timing in the multiplexer.

2. A signal reception device for receiving and demodulating an optical signal modulated by a Differential Quadrature Phase Shift Keying (DQPSK) modulation scheme, said signal reception device comprising:

a front end including two delay interferometers and opto-electric conversion elements that receives the DQPSK optical signal and converts the DQPSK optical signal into an in-phase signal and a quadrature-phase signal;

a clock and data recovery that regenerates a clock and a data signal based on the in-phase signal and the quadrature-phase signal;

a multiplexer that multiplexes the in-phase signal and the quadrature-phase signal output from the clock and data recovery;

a reception frame processing unit that detects frame synchronization based on the signal multiplexed by the multiplexer; and

a controller that, based on a detection result from the reception frame processing unit indicating an out-of-frame-synchronization state, controls logical inversion operations in the clock and data recovery, controls a multiplexing timing in the multiplexer, and controls the delay interferometers in the front end.

3. The signal reception device as claimed in claim 1 or 2 , wherein the reception frame processing unit comprises:

a frame processor that performs a frame synchronization pull-in operation and a frame de-mapping operation;

a frame synchronization circuit that detects a synchronization bit string in the multiplexed signal obtained by multiplexing the in-phase signal and the quadrature-phase signal in the multiplexer, and performs frame synchronization detections;

a register that stores combinations of plural of the synchronization bit strings; and

an identification section that, based on the synchronization bit strings of the multiplexed signal and the synchronization bit strings stored in the register, identifies a signal reception state, and notifies the controller of the signal reception state.

4. The signal reception device as claimed in claim 1 or 2 , wherein:

the controller, based on the signal reception state identification information, determines whether a detected signal reception state is an object state, whether the detected signal reception state is a state convertible to the object state by the logical inversion control, or whether the detected signal reception state is a state convertible to the object state by the logical inversion control and the multiplexing timing control;

the controller does not perform control operations when the detected signal reception state is the object state;

the controller controls the clock and data recovery to perform the logical inversion control when the detected signal reception state is a state convertible to the object state by the logical inversion control; and

the controller controls the clock and data recovery to perform the logical inversion control and controls the multiplexer to perform the multiplexing timing control when the detected signal reception state is a state convertible to the object state by the logical inversion control and the multiplexing timing control.

5. The signal reception device as claimed in claim 1 or 2 , further comprising:

an in-phase detector configured to detect whether a quadrature phase relation holds based on exclusive OR logic between the in-phase signal and the quadrature-phase signal input to the multiplexer;

wherein

the controller shifts a phase of the delay interferometers by π/2 or −π/2 based on detection results of the in-phase detector.

6. The signal reception device as claimed in claim 1 or 2 , wherein the reception frame processing unit comprises:

at least one of a logic inversion circuit that performs logic inversion of input data according to a logic inversion control signal from the controller and a neighboring bit exchanging circuit that exchanges neighboring bits of the input data.

7. The signal reception device as claimed in claim 1 or 2 , wherein according to a logic inversion control signal from the controller, the reception frame processing unit performs logic inversion control on an in-phase signal component and a quadrature-phase signal component output from the front end, independently.

8. The signal reception device as claimed in claim 1 or 2 , wherein the reception frame processing unit comprises:

a frame processor that performs a frame synchronization pull-in operation and a frame de-mapping operation;

a frame synchronization circuit including a plurality of frame synchronization units, each of said frame synchronization units receiving a synchronization bit string in the multiplexed signal and performing frame synchronization detections corresponding to respective combinations of plural of the synchronization bit strings; and

an identification section that identifies a signal reception state depending on which one of the frame synchronization units a detection signal is output from, and notifies the controller of information of the signal reception state identification.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2006
From: KATAGIRI, TORU; HOSHIDA, TAKESHI; TAKAHARA, TOMOO; NAKAMURA, KENTARO; KUWATA, NAOKI
To: FUJITSU LIMITED
Reel/Frame 018644/0971 →
Priority Claims (3)
JP 2005-054371 · Feb 28, 2005 · national
JP 2005-206467 · Jul 15, 2005 · national
JP 2006-116291 · Apr 20, 2006 · national
Continuity (2)
Continuation In Part 1128288600 · Nov 21, 2005
Related Publication 20070065157A1 · Mar 22, 2007