IP Library Granted Patent US 7,689,403
Granted Patent B2
US 7,689,403 · App. 12/148,205 · Granted Mar 30, 2010

Instructions providing new functionality for utilization by a target system program of host system container words during computer system emulation with host word size larger than that of the emulated machine

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,689,403
App. No.
12/148,205
Granted
Mar 30, 2010
Kind
B2
Abstract

Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

Claims (21)

1. In a data processing system in which the structure and operation of a target computer system is emulated by an emulation program on a host computer system and target system memory words, each having a number of bits that are stored within host system memory words, and wherein the number of bits in each of the target system memory words is less than the number of bits in each of the host system memory words, a process for providing target system program accessibility to complete host system memory words which enables newly defined target system functionality comprising the steps of:

A) storing in host system memory target system words such that each target system word is contained within, but does not fill, a host system word, and

B) aligning a plurality of target system words within the same plurality of host system words such that there is a region of normally utilized bits for containing each target system word within each of the plurality of host system words, and leaving within each of this plurality of host system words a remaining number of bits, and

C) in response to a first target system instruction, invoking first newly defined target system functionality specified by the first target system instruction to be provided by the emulation program during emulation of the target system program by:

1) forming a first address of a first host system memory word, and

2) providing for reading by the target system program a first content of said first host system word including in the first content all of the bits of the first host system memory word, including those normally utilized and also those remaining bits within the first host system memory word, and

D) in response to a second target system instruction invoking second newly defined target system functionality specified by the second target system instruction to be provided by the emulation program during emulation of a target system program by,

1) forming a second address of a second host system memory word, and

2) providing for writing by the target system program into all bits of the host system memory word including writing into both the normally utilized bits and also the remaining bits of the second host system memory word.

2. In a data processing system in which the structure and operation of a target computer system is emulated by an emulation program on a host computer system and target system memory words, each having a number of bits that are stored within host system memory words, and wherein the number of bits in each of the target system memory words is less than the number of bits in each of the host system memory words, a process for providing target system program accessibility to complete host system memory words comprising the steps of:

A) storing in host system memory target system words such that each target system word is contained within, but does not fill, a host system word, and

B) aligning a plurality of target system words within the same plurality of host system words such that there is a region of normally utilized bits for containing each target system word within each of the plurality of host system words, and leaving within each of this plurality of host system words a remaining number of bits, and

C) in response to a target system instruction invoking newly defined target system functionality specified by the first target system instruction to be provided by the emulation program during emulation of a target system program:

1) forming an address of a host system memory word, and

2) providing for reading by the target system program content of the host system word including in the content all the bits of the host system memory word, including those normally utilized and also those remaining bits within the host system memory word.

3. In a data processing system in which the structure and operation of a target computer system is emulated by an emulation program on a host computer system and target system memory words, each having a number of bits that are stored within host system memory words, and wherein the number of bits in each of the target system memory words is less than the number of bits in each of the host system memory words, a process for providing target system program accessibility to complete host system memory words comprising the steps of:

A) storing in host system memory target system words such that each target system word is contained within, but does not fill, a host system word, and

B) aligning a plurality of target system words within the same plurality of host system words such that there is a region of normally utilized bits for containing each target system word within each of the plurality of host system words, and leaving within each of this plurality of host system words a remaining number of bits, and

C) in response to a target system instruction invoking newly defined target system functionality specified by the target system instruction to be provided by the emulation program during emulation of a target system program,

1) forming an address of a host system memory word, and

2) provide for writing by the target system program into all bits of the host system memory word, including writing into both the normally utilized and also the remaining bits of the host system memory word.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 19, 2026
From: BULL HN INFORMATION SYSTEMS INC.; ATOS IT SOLUTIONS AND SERVICES, INC.
To: ATOS IT SOLUTIONS AND SERVICES, INC.
Reel/Frame 073507/0458 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2026
From: ATOS IT SOLUTIONS AND SERVICES, INC.
To: EVIDEN USA, INC.
Reel/Frame 073507/0609 →
Continuity (2)
Continuation 1100641400 · Dec 7, 2004
Related Publication 20080208562A1 · Aug 28, 2008