Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system
A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
1. A method of transferring a stream of data from a first clock domain with a first clock signal to a second clock domain with a second clock signal, wherein the first and second clock signals have a mesochronous relationship, the method comprising the acts of:
receiving the data stream;
sampling the first clock signal in the second clock domain;
in response to the sampling of the first clock signal, forming a modified version of the first clock signal, the modified version of the first clock signal having a known phase relationship to the second clock signal;
forming a parallel form of the received data under the control of the modified version of the first clock signal;
in response to the sampling of the first clock signal, selecting a subset of contiguous bits of the parallel data for use in the second clock domain.
2. The method of claim 1 wherein an input signal is received, wherein the received data and the first clock are embedded in the input signal, and wherein the data and first clock signal are extracted from the input signal.
3. The system of claim 2 wherein the first clock signal is sampled with a flip flop and wherein the first clock is modified in increments of the frequency of the clock signal embedded in the input signal.