Multi-level memory cell having phase change element and asymmetrical thermal boundary

1. An integrated circuit memory, comprising:

an array of memory cells including access circuitry, memory cells in the array respectively comprising:

a memory material switchable between a lower resistivity phase and a higher resistivity phase by application of current, the memory material being coupled to first and second electrodes in respective first and second contact areas which define an electric field region within the memory material between the first and second electrodes, the memory material having first and second boundaries between the first and second contact areas, and wherein the first and second electrodes are coupled to the access circuitry; and

first and second thermal isolation materials in heat-conducting relation to the first and second boundaries of the memory material, the first and second thermal isolation materials having different thermal conductivity properties such that heat flow out of the electric field region through the first and second boundaries in the memory material is asymmetrical.

2. The integrated circuit memory of claim 1 , further comprising:

a controller coupled to the array, including resources for applying current to a selected memory cell, the current configured to induce formation of a combination of the lower resistivity phase and the higher resistivity phase in the memory material within the electric field region, the combination establishing a gradient from lower resistivity near the first boundary to higher resistivity near the second boundary to set a resistance for the memory cell between the first and second electrodes.

3. The integrated circuit memory of claim 2 , wherein the controller is configured to apply a pulse configuration inducing current in the memory cell to program the memory cell to a determined value corresponding to a reset state, causing formation of the higher resistivity phase in substantially all of an active volume the memory material.

4. The integrated circuit memory of claim 2 , wherein the controller is configured to determine a data value including at least two bits, for a selected memory cell; and to apply a pulse configuration according to the determined data value that establishes a gradient setting the resistance of the memory cell within a range of resistance corresponding to the determined data value.

5. The integrated circuit memory of claim 1 , wherein:

the first and second electrodes each have a top side;

a first insulating member between the first and second electrodes comprises the first thermal isolation material;

a thin film bridge comprising the memory material crosses the insulating member and defines an inter-electrode path between the first and second electrodes near the top sides of the first and second electrodes; and

a second insulating member overlying the thin film bridge comprises the second thermal isolation material.

6. An integrated circuit memory, comprising:

an array of memory cells including access circuitry, memory cells in the array respectively comprising:

a memory material switchable between a lower resistivity phase and a higher resistivity phase by application of current, the memory material being coupled to first and second electrodes in respective first and second contact areas which define an electric field region within the memory material between the first and second electrodes, the memory material having first and second boundaries between the first and second contact areas, and wherein the first and second electrodes are coupled to the access circuitry; and

first and second thermal isolation materials in heat-conducting relation to the first and second boundaries of the memory material, the first and second thermal isolation materials having different thermal conductivity properties such that heat flow out of the electric field region through the first and second boundaries in the memory material is asymmetrical; and

a controller coupled to the array, including resources for applying current to a selected memory cell, the current configured to induce formation of a combination of the lower resistivity phase and the higher resistivity phase in the memory material within the electric field region, the combination establishing a gradient from lower resistivity near the first boundary to higher resistivity near the second boundary to set a resistance for the memory cell between the first and second electrodes, and wherein:

the first electrode has a top side and the second electrode has a bottom side, and

the memory material is situated between the top side of the first electrode and the bottom side of the second electrode, defining an inter-electrode path between the first and second electrodes; and

the first thermal isolation material is in heat-conducting relation to the first boundary of the memory material and the second thermal isolation material is in heat-conducting relation to the second boundary of the memory material.

7. The integrated circuit memory of claim 1 , wherein the first and second thermal insulating materials comprise respective co-planar thin films which abut along a seam, and the memory elements comprise phase change material within pores along the seam and contact bottom electrodes beneath the co-planar thin films.

8. The integrated circuit memory of claim 1 , wherein the first contact area is substantially smaller than the second contact area.

9. The integrated circuit memory of claim 1 , wherein the first and second thermal insulating materials comprise respective co-planar thin films which abut along a seam, and the first electrodes comprise conductive members within pores along the seam, and contact the first contact areas on the memory material over the co-planar thin films, wherein the first contact area is substantially smaller than the second contact area; and

the memory material comprising strips of programmable resistance material that cross the seam over the first electrodes.