Scan compression architecture for a design for testability compiler used in system-on-chip software design tools
A scan compression architecture for a design for a testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset of the pins. The first scan architecture is selectively enabled for executing a scan test with a low time. The second scan architecture is for executing a scan test with high parallelism.
1. A scan compression architecture for a design for a test compiler used in a system-on-chip software design tool comprising:
a plurality of pins;
a first scan configuration architecture comprising a first scan compressor/decompressor configuration connected to said plurality of pins; and
a second scan architecture comprising a second scan compressor/decompressor configuration connected to a subset of said plurality of pins;
said first scan architecture being enabled for executing a first scan test with a lower test time as compared to executing the first scan test with said second scan architecture, and said second scan architecture being enabled for executing a second scan test with a higher parallelism as compared to executing the second scan test with said first scan architecture.
2. A scan compression architecture according to claim 1 wherein said first scan architecture and said second scan architecture are selectively enabled by an external control signal.
3. A scan compression architecture according to claim 2 wherein said plurality of pins comprises an input pin; and wherein the external control signal is received on the input pin.
4. A scan compression architecture according to claim 1 wherein each of said first and second scan compressor/decompressor configurations is enabled or bypassed for providing two corresponding operating modes.
5. A scan compression architecture according to claim 1 wherein said plurality of pins comprises a plurality of input and output pins; and further comprising a single logic core connected to said plurality of input and output pins; and wherein said first scan compressor/decompressor configuration comprising a first plurality of scan chains, and said second scan compressor/decompressor configuration comprising a second plurality of scan chains.
6. A scan compression architecture according to claim 5 further comprising:
a multiplexer coupled between said plurality of output pins and said single logic core; and
a demultiplexer coupled between said single logic core and said plurality of input;
said multiplexer and said demultiplexer being configured based on a control signal for mapping said first and second plurality of scan chains for said first and second scan compressor/decompressor configurations.
7. A scan compression architecture according to claim 6 wherein operating modes of said first and second scan compressor/decompressor configurations are based on an additional control signal.
8. A scan compression architecture according to claim 7 wherein the operating modes include a first operating mode for selecting scan test patterns associated with said first scan compressor/decompressor configuration, and a second operating mode for selecting scan test patterns associated with said second scan compressor/decompressor configuration, said first scan compressor/decompressor configuration being connected to all of said plurality of input and output pins, and said second scan compressor/decompressor configuration being connected to a portion of said plurality of input and output pans.
9. A scan compression architecture according to claim 8 wherein the control signal and the additional control signal are generated internally based on a JTAG IEEE 1149.1 standard architecture.
10. A scan compression architecture according to claim 8 wherein said plurality of input pins are shared between the first and second operating modes.
11. A scan compression architecture according to claim 8 the first operating mode corresponds to a package level test and the second operating mode corresponds to an electrical wafer level test.
12. A scan compression architecture according to claim 1 further comprising at least one additional scan compressor/decompressor configuration connected to a second subset of said plurality of pins, said at least one additional scan compressor/decompressor configuration being enabled for executing a scan test with predetermined parallelism.
13. A test complier comprising:
a plurality of pins;
a first scan compressor/decompressor configuration connected to said plurality of pins; and
a second scan compressor/decompressor configuration connected to a subset of said plurality of pins;
said first scan compressor/decompressor configuration being enabled for executing a first scan test with a lower test time as compared to executing the first scan test with said second scan compressor/decompressor configuration, and said second scan compressor/decompressor configuration being enabled for executing a second scan test with a higher parallelism as compared to executing the second scan test with said first scan compressor/decompressor configuration.
14. A test complier according to claim 13 wherein said first scan compressor/decompressor configuration and said second scan compressor/decompressor configuration are selectively enabled by an external control signal.
15. A test complier according to claim 14 wherein said plurality of pins comprises an input pin; and wherein the external control signal is received on the input pin.
16. A test complier according to claim 13 wherein each of said first and second scan compressor/decompressor configurations is enabled or bypassed for providing two corresponding operating modes.
17. A test complier according to claim 13 wherein said plurality of pins comprises a plurality of input and output pins; and further comprising a single logic core connected to said plurality of input and output pins; and wherein said first scan compressor/decompressor configuration comprising a first plurality of scan chains, and said second scan compressor/decompressor configuration comprising a second plurality of scan chains.
18. A test complier according to claim 17 further comprising:
a multiplexer coupled between said plurality of output pins and said single logic core; and
a demultiplexer coupled between said single logic core and said plurality of input;
said multiplexer and said demultiplexer being configured based on a control signal for mapping said first and second plurality of scan chains for said first and second scan compressor/decompressor configurations.
19. A test complier according to claim 18 wherein operating modes of said first and second scan compressor/decompressor configurations are based on an additional control signal.
20. A test complier according to claim 19 wherein the operating modes include a first operating mode for selecting scan test patterns associated with said first scan compressor/decompressor configuration, and a second operating mode for selecting scan test patterns associated with said second scan compressor/decompressor configuration, said first scan compressor/decompressor configuration being connected to all of said plurality of input and output pins, and said second scan compressor/decompressor configuration being connected to a portion of said plurality of input and output pins.
21. A test complier according to claim 20 wherein the control signal and the additional control signal are generated internally based on a JTAG IEEE 1149.1 standard architecture.
22. A test complier according to claim 20 wherein said plurality of input pins are shared between the first and second operating modes; and wherein the first operating mode corresponds to a package level test and the second operating mode corresponds to an electrical wafer level test.
23. A method for providing a scan compression architecture through a design for testability compiler used in a system-on-chip, the method comprising:
connecting a first scan compressor/decompressor configuration to a plurality of pins; and
connecting a second scan compressor/decompressor configuration to a subset of the plurality of pins;
the first scan compressor/decompressor configuration being enabled for executing a first scan test with a lower test time as compared to executing the first scan test with the second scan compressor/decompressor configuration, and the second scan compressor/decompressor configuration being enabled for executing a second scan test with a higher parallelism as compared to executing the second scan test with the first scan compressor/decompressor configuration.
24. A method according to claim 23 wherein the first scan compressor/decompressor configuration and the second scan compressor/decompressor configuration are selectively enabled by an external control signal.
25. A method according to claim 24 wherein the plurality of pins comprises an input pin; and wherein the external control signal is received on the input pin.
26. A method according to claim 23 wherein each of the first and second scan compressor/decompressor configurations is enabled or bypassed for providing two corresponding operating modes.
27. A method according to claim 23 wherein the plurality of pins comprises a plurality of input and output pins; and further comprising a single logic core connected to the plurality of input and output pins; and wherein the first scan compressor/decompressor configuration comprises a first plurality of scan chains, and the second scan compressor/decompressor configuration comprises a second plurality of scan chains.
28. A method according to claim 27 wherein the scan compression architecture further comprises a multiplexer coupled between the plurality of output pins and the single logic core; and a demultiplexer coupled between the single logic core and the plurality of input; the multiplexer and the demultiplexer being configured based on a control signal for mapping the first and second plurality of scan chains for the first and second scan compressor/decompressor configurations.
29. A method according to claim 28 wherein operating modes of the first and second scan compressor/decompressor configurations are based on an additional control signal.
30. A method according to claim 29 wherein the operating modes include a first operating mode for selecting scan test patterns associated with the first scan compressor/decompressor configuration, and a second operating mode for selecting scan test patterns associated with the second scan compressor/decompressor configuration, the first scan compressor/decompressor configuration being connected to all of the plurality of input and output pins, and the second scan compressor/decompressor configuration being connected to a portion of the plurality of input and output pins.
31. A method according to claim 30 wherein the plurality of input pins are shared between the first and second operating modes; and wherein the first operating mode corresponds to a package level test and the second operating mode corresponds to an electrical wafer level test.