Method of algorithmic analog-to-digital conversion and algorithmic analog-to-digital converter

1. An algorithmic Analog-To-Digital converter (ADC) having an external ADC circuit and a Multiplying Digital-to-Analog Converter (MDAC), the MDAC comprising:

a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal;

a subtractor for calculating a difference between the signal output from the DAC and an analog signal output from a first Sample and Hold Amplifier (SHA);

an amplifier for amplifying the difference;

a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit;

a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit; and

a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit,

wherein the first capacitor is configured to receive a signal from the first SHA and output the signal to the amplifier to be amplified,

wherein the amplifier is configured to output the amplified signal to the second capacitor and to the external ADC circuit, so that the amplified signal stored in the second capacitor can be feedback to the amplifier and an output from the external ADC circuit can be provided to the second capacitor, and

wherein the third capacitor is configured to receive an output signal from the amplifier, where the output signal is generated by the amplifier according to the feedback signal received from the second capacitor.

2. The algorithmic ADC of claim 1 , wherein the first SHA receives the analog signal, and samples and holds the analog signal.

3. The algorithmic ADC of claim 1 , further comprising:

a plurality of external ADC circuits, each external ADC circuit being configured to convert an analog signal output from the MDAC into a digital signal and output the first-digital signal to the MDAC.

4. The algorithmic ADC of claim 1 , wherein the MDAC further comprises: a second SHA for sampling and holding an analog signal input from outside to the MDAC.

5. The algorithmic ADC of claim 3 , further comprising: a digital error correction logic for receiving the signal output from the flash ADC and correcting an error of the signal.

6. The algorithmic ADC of claim 1 , wherein the first, second and third switching units operate according to a clock signal received from outside.

7. The algorithmic ADC of claim 1 , further comprising: a clock generator for providing a clock signal to the respective switching units.

8. The algorithmic ADC of claim 7 , wherein the clock generator generates a clock signal using a Phase-Locked Loop (PLL) circuit and divides the clock signal into clock signals corresponding to the respective switching units using at least one divider.

9. A method of algorithmic analog-to-digital conversion, comprising:

receiving an analog signal, sampling the analog signal at a Sample and Hold Amplifier (SHA), and storing the analog signal in a first capacitor unit;

inputting the signal stored in the first capacitor unit to an amplifier, and storing a signal amplified by the amplifier in a second capacitor unit;

inputting the signal stored in the second capacitor unit to the amplifier, storing a signal amplified by the amplifier in a third capacitor unit, and outputting the amplified signal to a flash Analog-to-Digital Converter (ADC);

calculating a difference between a signal received from the flash ADC and the signal stored in the third capacitor unit, and storing the difference in the third capacitor unit again;

inputting the signal stored in the third capacitor unit to the amplifier, storing an output amplified by the amplifier in the second capacitor unit, and outputting the output to the flash ADC;

calculating a difference between a signal received from the flash ADC and the signal stored in the second capacitor unit, and storing the difference in the second capacitor unit again; and

inputting the signal stored in the second capacitor unit to the amplifier, storing an output amplified by the amplifier in the third capacitor unit, and outputting the output to the flash ADC.

10. The method of claim 9 , wherein inputting the signal stored in the third capacitor unit to the amplifier, storing an output amplified by the amplifier in the second capacitor unit, and outputting the output to the flash ADC;

calculating a difference between a signal received from the flash ADC and the signal stored in the second capacitor unit, and storing the difference in the second capacitor unit again; and inputting the signal stored in the second capacitor unit to the amplifier, storing an output amplified by the amplifier in the third capacitor unit, and outputting the output to the flash ADC are repeatedly performed according to a digital resolution.

11. The method of claim 9 , wherein a repetition period of inputting the signal stored in the third capacitor unit to the amplifier, storing an output amplified by the amplifier in the second capacitor unit, and outputting the output to the flash ADC is larger than a repetition period of calculating a difference between a signal received from the flash ADC and the signal stored in the second capacitor unit, and storing the difference in the second capacitor unit again, and the repetition period of calculating a difference between a signal received from the flash ADC and the signal stored in the second capacitor unit, and storing the difference in the second capacitor unit again is larger than a repetition period of inputting the signal stored in the second capacitor unit to the amplifier, storing an output amplified by the amplifier in the third capacitor unit, and outputting the output to the flash ADC.

12. The method of claim 9 , wherein repetition periods of inputting the signal stored in the third capacitor unit to the amplifier, storing an output amplified by the amplifier in the second capacitor unit, and outputting the output to the flash ADC to inputting the signal stored in the second capacitor unit to the amplifier, storing an output amplified by the amplifier in the third capacitor unit, and outputting the output to the flash ADC are generated by a Phase-Locked Loop (PLL) circuit and correspond to clock periods divided by at least one divider.

13. The method of claim 9 , wherein the first capacitor unit IS connected with the SHA and an input end of the amplifier through a switch, and the switch is operated by a clock signal received from outside.

14. The method of claim 9 , wherein the second and third capacitor units are connected with an input end and an output end of the amplifier through a switch, and the switch is operated by a clock signal received from outside.