Electronic device with uniform-resistance fan-out blocks

1. An electronic device comprising:

a plurality of first leads;

a plurality of second leads; and

at least two fan-out blocks adjacent to each other and respectively connected between the first leads and the second leads, each of said fan-out blocks comprising a plurality of interconnecting leads, each of the interconnecting leads having:

a first routing portion coupled to one of the first leads;

a second routing portion coupled to one of the second leads; and

an intermediate portion located between the first routing portion and the second routing portion, the intermediate portion and the second routing portion meeting at an intersection point, wherein a segment between the intersection point and the second lead is defined as an intercept length of the second routing portion;

wherein the intercept lengths of the second routing portions of two adjacent outmost interconnecting leads of said adjacent fan-out blocks are different.

2. The electronic device as claimed in claim 1 , wherein the second routing portion of each of said interconnecting leads has routing trace style of a straight line, a bow-shaped line, a zigzag line, a serpentine line, or a combination thereof.

3. The electronic device as claimed in claim 1 , wherein the first routing portion of each of said interconnecting leads has routing trace style of a straight line, a bow-shaped line, a zigzag line, a serpentine line, or a combination thereof.

4. The electronic device as claimed in claim 1 , wherein said electronic device is an LCD panel, said first leads connecting with a plurality of bonding pads in a bonding area of said LCD panel.

5. The electronic device as claimed in claim 4 , wherein said second leads comprise data lines of said LCD panel.

6. The electronic device as claimed in claim 4 , wherein said second leads comprise gate lines of said LCD panel.

7. The electronic device as claimed in claim 1 , wherein difference in resistance between said two adjacent outmost interconnecting leads in said adjacent fan-out blocks is less than 10Ω.

8. The electronic device as claimed in claim 1 , wherein said interconnecting leads in each of said fan-out blocks have uniform resistance.

9. The electronic device as claimed in claim 8 , wherein a ratio of maximum resistance to minimum resistance of said interconnecting leads in each of said fan-out blocks is less than 3.

10. A method of generating a circuit on a substrate, the circuit having uniform resistance for an electronic device, the method comprising:

providing a plurality of first leads and a plurality of second leads;

constructing a first fan-out block connecting between the first leads and the second leads, said first fan-out block comprising a plurality of interconnecting leads, each of the interconnecting leads having:

a first routing portion coupled to one of the first leads;

a second routing portion coupled to one of the second leads; and

an intermediate portion located between the first routing portion and the second routing portion, the intermediate portion and the second routing portion meeting at an intersection point, wherein a segment between the intersection point and the second lead is defined as an intercept length of the second routing portion;

constructing a second fan-out block adjacent to said first fan-out block, wherein the intercept lengths of the second routing portions of two adjacent outmost interconnecting leads in said second fan-out block and said first fan-out block are different; and

constructing routing in the second routing area and the first routing area in said second fan-out block.

11. The method as claimed in claim 10 , wherein said electronic device is an LCD panel, said first leads connecting with a plurality of bonding pads in a bonding area of said LCD panel.

12. The method as claimed in claim 10 , wherein the second routing portion of each of said interconnecting leads has routing trace style of a straight line, a bow-shaped line, a zigzag line, a serpentine line, or a combination thereof.

13. The method as claimed in claim 10 , wherein said routing in the second routing area is constructed before said routing in the first routing area.

14. The method as claimed in claim 10 , wherein said routing in the second routing area is constructed after said routing in the first routing area.

15. The method as claimed in claim 10 , wherein:

if the outmost interconnecting lead in said second fan-out block has a resistance less than the resistance of the outmost interconnecting lead in said first fan-out block, then the intercept length of the outmost interconnecting lead in said second fan-out block is longer than the intercept length of the outmost interconnecting lead in said first fan-out block; and

if the outmost interconnecting lead in said second fan-out block has a resistance larger than the resistance of the outmost interconnecting lead in said first fan-out block, then the intercept length of the outmost interconnecting lead in said second fan-out block is shorter than the intercept length of the outmost interconnecting lead in said first fan-out block.

16. The method as claimed in claim 10 , wherein difference in resistance between said two adjacent outmost interconnecting leads in said first fan-out block and said second fan-out block is less than 10Ω.

17. The method as claimed in claim 10 , wherein said interconnecting leads have uniform resistance respectively in said first fan-out block and said second fan-out block.

18. The method as claimed in claim 17 , wherein a ratio of maximum resistance to minimum resistance of said interconnecting leads is less than 3 respectively in said first fan-out block and said second fan-out block.