Static random access memory

1. A static random access memory comprising:

a. a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground;

b. a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and

c. a switch for selectively connecting and disconnecting the ground node of the second inverter to and from ground; and

wherein each inverter has a Q node and a QB node, and the memory further comprises:

d. a bit-line;

e. a write switch for selectively connecting the bit line to the Q nodes of the inverters during a write operation; and

f. a pair of read switches connected in series between the bit line and ground, the read switches comprising:

i. a first read switch controlled by a read signal; and

ii. a second read switch controlled by the voltage at the QB nodes of the inverters.

2. The memory of claim 1 wherein the read switches are transistors.

3. The memory of claim 1 wherein the read switches are MOSFETs.

4. A method of operating a static random access memory, the memory comprising a pair of cross-coupled inverters each having a supply voltage node connected to a supply voltage, and a ground node connected to ground, the method comprising disconnecting the ground node of one of the inverters from ground during a write operation; and wherein each inverter has a Q node and a QB node, the method further comprising:

a. writing from a bit line to the Q nodes of the inverters during a write operation;

b. pre-charging the bit line prior to the read operation; and

c. connecting the bit line to ground during the read operation if the voltage at the QB nodes is high.